Error Running/Debugging STLink after update to Eclipse/STM components
Everything has been running and working for the last year and I have done a few updates but decided to update everything this morning and now after the “April 2018” Eclipse update along with the STM compiler and such I cannot upload new firmware or debug. It complains about the target voltage being too low. This has not been a problem before and I am using the SWD connection from an eval board to the board I designed. I checked the .cfg file and it does have a line that shows Enable Low power but I don’t think that is related. Any thoughts on something I can update in the config to get past this error?
Open On-Chip Debugger 0.10.0-dev-00010-g96aab7b (2018-07-13-06:43)
Licensed under GNU GPL v2
For bug reports, read
http://openocd.org/doc/doxygen/bugs.html
srst_only separate srst_nogate srst_open_drain connect_assert_srst
Info : The selected transport took over low-level target control. The results might differ compared to plain JTAG/SWD
adapter_nsrst_delay: 100
adapter speed: 950 kHz
Info : clock speed 950 kHz
Info : STLINK v2.1 JTAG v28 API v2 M17 VID 0x0483 PID 0x374B
Info : using stlink api v2
Info : Target voltage: 0.006353
__Error: target voltage may be too low for reliable debugging
Error: init mode failed (unable to connect to the target)__
Config file:
- This is an NUCLEO-F303RE board with a single STM32F303RETx chip
- Generated by System Workbench for STM32
- Take care that such file, as generated, may be overridden without any early notice. Please have a look to debug launch configuration setup(s)
source find interface/stlink.cfg
set WORKAREASIZE 0x8000
transport select “hla_swd”
set CHIPNAME STM32F303RETx
set BOARDNAME NUCLEO-F303RE
- Enable debug when in low power modes
set ENABLE_LOW_POWER 1
- Stop Watchdog counters when halt
set STOP_WATCHDOG 1
- STlink Debug clock frequency
set CLOCK_FREQ 4000
- use hardware reset, connect under reset
- connect_assert_srst needed if low power mode application running (WFI...)
reset_config srst_only srst_nogate connect_assert_srst
set CONNECT_UNDER_RESET 1
source find target/stm32f3x.cfg
;){kind=link}