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SW4STM32 and SW4Linux fully supports the STM32MP1 asymmetric multicore Cortex/A7+M4 MPUs

   With System Workbench for Linux, Embedded Linux on the STM32MP1 family of MPUs from ST was never as simple to build and maintain, even for newcomers in the Linux world.
And, if you install System Workbench for Linux in System Workbench for STM32 you can seamlessly develop and debug asymmetric applications running partly on Linux, partly on the Cortex-M4.
You can get more information from the ac6-tools website and download two short videos (registration required) highlighting:

System Workbench for STM32

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You are viewing a reply to ldmia instruction is causing an exception on Nucleo-F103RB board  

ldmia instruction is causing an exception on Nucleo-F103RB board

Posted by dautrevaux on 2018-12-17 14:20 France

Hi,

Where is data located? Is it close to the end of memory? Does it work also with {r0-r4} (as many registers that {r4-r8} ?

The xPSR should not have any effect there so changing it could not solve your problem; we really need a bit more information on your problem to help but the only thing I could think of is:

  1. The alignment of data (is it correctly 4-byte aligned?)
  2. The size of the transfer (is there effectively 5*4 = 20 bytes of data there).


Regarding the CPSR, which on a Cortex-M is in fact the xPSR, it does not have to be initialized and the core is executing in privileged thread mode on reset, and stay in this mode unless the CONTROL register is modified to switch to non-privileged mode (but neither HAL nor StdPeriph or even FreeRTOS change that).

Bernard (Ac6)
Bernard (Ac6)

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