That worked for me as well, at 4 MHz. So my problem wasn’t a signal integrity issue. The chip has 0x5000 of RAM, so I’m not sure how the default debug workarea size of 0x5000 would work in any case, since I gather from this source that the working area should be some free RAM that can be used by the debugger, and would presumably need to be smaller than (physical size - application size). It’s also not clear to me how the debug interface speed plays into this. Guessing here, but maybe the work area gets disabled if it’s set to be >= the whole chip SRAM size, and the SRAM work area is needed to speed things up enough to support the full speed?