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    • APSR (Application Processor Status Register)

    Posted by Guy on 2019-02-20 17:08

    Hello all,
    Is there a way to view the APSR (Application Processor Status Register)
    Thanks

    Reads: 8512
    Posted by ayoub.bourjilat on 2019-02-20 17:49 France

    Hi,

    You can access to the APSR in the debug view (registers) by reading xPSR register (which combine the APSR, IPSR and EPSR) so the 31 to 27 bits are the N, Z, C, V, Q respectively. If you want to get the APSR Values in the code you can use the __get_APSR().

    Best regards,
    Ayoub
    AC6

         Posted by Guy on 2019-02-21 09:56

    Thanks,

    I got a random and very seldom issue with a vcmpe comparison and the following branch is not correct.
    It is why I asked to see the APSR register.
    I my case the result of the vcmpe should set the N flag but at the point the debugger stop the N flag is 0 confirmed by the ble branch not executed.
    I used eCos os, STM32F429

    Regards,

    Doc1.docx (772.64 Kb)
    Posted by ayoub.bourjilat on 2019-02-21 10:29 France

    Hi,

    What do you mean by random ?
    The value in s15 should be equal to s14 ?

    Regards,
    Ayoub

         Posted by Guy on 2019-02-21 10:55

    Hi Ayoub,

    The code runs each seconds and sometimes I get this behavior (once a day, once a week).
    In the case of the breakpoint s14=50 s15=4.1366
    vcmpe s15, s14 should set the flags based on s15-s14 which gives a negative value so the N flag=1
    but the ble (branch if Less or Equal) does not jump confirmed by the APSR bits 28 to 31 = 0
    so the vcmpe has not set the flag or the flag has disapeared for unknown reason that I try to understand

    Best regards

         Posted by ayoub.bourjilat on 2019-02-21 12:01 France


    First ,you can check the bit 31 in the FPSCR after the execution of the vmcpe (in the assembly view)
    vmcpe set the flags in the FPSCR and after copy the values NZCV to APSR.

    Second, you can use the Instruction Synchronization Barrier (ISB --> __ISB()) to flush the pipeline in the processor so that all instructions following the ISB are fetched from cache or memory after the instruction has completed. It ensures that the effects of context altering operations and any branches that appear in program order after it (the ISB) are always written into the branch prediction logic with the context that is visible after the ISB instruction (this will ensure correct execution of the instruction stream)

    Best regards,
    Ayoub
    AC6

         Posted by Guy on 2019-02-21 14:31

    Thanks Ayoub,

    This is random and seldom, so 99.9999% the flags will be set correctly by the vmcpe.
    All my code is C or C++.
    the original code was
    if (m_fCoor_I > 50.0F)
    m_fCoor_I = 50.0F;
    does it means I need to integrate the __ISB() instruction before each floating point comparaisons because I have many.

    As a workaround I modified to have the comparison in integer
    long int lCorr = m_fCorr_I;
    if (lCorr > 50)
    m_fCorr_I=50.0F;

    Best regards


     
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