Loading...
 

SW4STM32 and SW4Linux fully supports the STM32MP1 asymmetric multicore Cortex/A7+M4 MPUs

   With System Workbench for Linux, Embedded Linux on the STM32MP1 family of MPUs from ST was never as simple to build and maintain, even for newcomers in the Linux world.
And, if you install System Workbench for Linux in System Workbench for STM32 you can seamlessly develop and debug asymmetric applications running partly on Linux, partly on the Cortex-M4.
You can get more information from the ac6-tools website and download two short videos (registration required) highlighting:

System Workbench for STM32


APSR (Application Processor Status Register)

Hello all,
Is there a way to view the APSR (Application Processor Status Register)
Thanks

France

Hi,

You can access to the APSR in the debug view (registers) by reading xPSR register (which combine the APSR, IPSR and EPSR) so the 31 to 27 bits are the N, Z, C, V, Q respectively. If you want to get the APSR Values in the code you can use the __get_APSR().

Best regards,
Ayoub
AC6

Thanks,

I got a random and very seldom issue with a vcmpe comparison and the following branch is not correct.
It is why I asked to see the APSR register.
I my case the result of the vcmpe should set the N flag but at the point the debugger stop the N flag is 0 confirmed by the ble branch not executed.
I used eCos os, STM32F429

Regards,

France

Hi,

What do you mean by random ?
The value in s15 should be equal to s14  ?

Regards,
Ayoub

Hi Ayoub,

The code runs each seconds and sometimes I get this behavior (once a day, once a week).
In the case of the breakpoint s14=50 s15=4.1366
vcmpe s15, s14 should set the flags based on s15-s14 which gives a negative value so the N flag=1
but the ble (branch if Less or Equal) does not jump confirmed by the APSR bits 28 to 31 = 0
so the vcmpe has not set the flag or the flag has disapeared for unknown reason that I try to understand

Best regards

France


First ,you can check the bit 31 in the FPSCR after the execution of the vmcpe (in the assembly view)
vmcpe set the flags in the FPSCR and after copy the values NZCV to APSR.

Second, you can use the Instruction Synchronization Barrier (ISB --> __ISB()) to flush the pipeline in the processor so that all instructions following the ISB are fetched from cache or memory after the instruction has completed. It ensures that the effects of context altering operations and any branches that appear in program order after it (the ISB) are always written into the branch prediction logic with the context that is visible after the ISB instruction (this will ensure correct execution of the instruction stream)

Best regards,
Ayoub
AC6

Thanks Ayoub,

This is random and seldom, so 99.9999% the flags will be set correctly by the vmcpe.
All my code is C or C++.
the original code was
if (m_fCoor_I > 50.0F)
m_fCoor_I = 50.0F;
does it means I need to integrate the __ISB() instruction before each floating point comparaisons because I have many.

As a workaround I modified to have the comparison in integer
long int lCorr = m_fCorr_I;
if (lCorr > 50)
m_fCorr_I=50.0F;

Best regards


 

Newest Forum Posts

  1. Can't download StdPeriph library during project creation by klopi90, 08:46
  2. Building project - subdir.mk error by nupurkohadkar1997, 2019-12-06 18:10
  3. openOCD Wrong device detected by maxim221, 2019-12-06 12:32
  4. STM32429I_Discovery board with printf float support problem by johannes.visser@msc-technologies.eu, 2019-12-05 16:08
  5. malloc heap issue with CubeMX Project by johannes.visser@msc-technologies.eu, 2019-12-05 16:04
  6. Debugger not working by Daniel Jack Morley, 2019-11-27 21:46
  7. Compiler change problem by Lucian Pop, 2019-11-20 17:41
  8. Sample programs and compiling by jjtimer, 2019-11-20 10:31
  9. Unit test issues for STM32 by Rinkedevries, 2019-11-18 10:32
  10. Ubuntu 19.04 Debug problems by costantino, 2019-11-17 19:17

Last-Modified Blogs