SW4STM32 and SW4Linux fully supports the STM32MP1 asymmetric multicore Cortex/A7+M4 MPUs

   With System Workbench for Linux, Embedded Linux on the STM32MP1 family of MPUs from ST was never as simple to build and maintain, even for newcomers in the Linux world.
And, if you install System Workbench for Linux in System Workbench for STM32 you can seamlessly develop and debug asymmetric applications running partly on Linux, partly on the Cortex-M4.
You can get more information from the ac6-tools website and download two short videos (registration required) highlighting:

System Workbench for STM32

You are viewing a reply to ADC/DMA transfer problem  

ADC/DMA transfer problem

The register bit names I use are the ones defined in the CMSIS headers - what you get if you #include “stm32f103xe.h” (or in my case, “stm32f091xc.h”)

I just took a quick look at the F103 ADC and it looks like it’s closer to the ADC on the F3 part than the one on the F0 series. You are correct that some of the register and bit names are different. The names may be a bit different (ADC1->CR1 instead of ADC1->CFGR1 for example) and the bit names are different in some cases too. When I was responding to your original request for help I was looking at the ADC code I had developed for my F091 project. I had to use different code for my F303 project, although it was based on the ADC library I created for the F0 ADC.

I apologize for the confusion this may have caused. I’ve not done much with the F1 series devices yet, and was operating under the (incorrect) assumption that the F1 ADC was the same as the one on the F0 parts.

I don’t use ADC interrupts in my F0 project(s), but I do test the interrupt status flags for the ADC in some places, as this is the only way to tell when certain events (end of conversion, end of sequence) occur. So I’m careful to explicitly clear the ADC1->ISR following init or prior to starting a new conversion.

I’m not certain just what generates the “trigger” for the DMA. It may be the EOC (end of conversion) ISR bit, it may be something else.