I use a STM32F103VE in a custom board.
ADC1 is started every ms and do 6 conversions in about 750µs. Results are transfered over DMA to RAM.
Sequenz ist started with this code:
DMA1_Channel1->CCR &= ~DMA_CCR_EN; // DMA-Transfer start new
DMA1_Channel1->CNDTR = 6;
DMA1_Channel1->CCR |= DMA_CCR_EN;
ADC1->CR2 |= ADC_CR2_ADON; // Start ADC1
After Start of DMA DMA1_Channel1->CNDTR counts to 5 and transfers last adc data to first RAM location.
Next five ADC conversions are transfered too end DMA ends while ADC do his last conversion.
So, first result in RAM isnt OK.
If I read ADC-DR before start of DMA, same result.
It seems DMA or ADC has a request stored and this request ist not to kill?
What is the solution for this problem?