SW4STM32 and SW4Linux fully supports the STM32MP1 asymmetric multicore Cortex/A7+M4 MPUs

   With System Workbench for Linux, Embedded Linux on the STM32MP1 family of MPUs from ST was never as simple to build and maintain, even for newcomers in the Linux world. And, if you install System Workbench for Linux in System Workbench for STM32 you can seamlessly develop and debug asymmetric applications running partly on Linux, partly on the Cortex-M4.
You can get more information from the ac6-tools website and download (registration required) various documents highlighting:

System Workbench for STM32

false condition if statement getting executed inside ISR


The simplest way to go, as you measure time between the last interrupt, is to just ignore any interrupt occuring less than x µs after a previous interrupt. Thus the first switch will be taken into account, then all bounce IRQs will be ignored waiting for at least x µs without any interrupt.

If you have ONLY one GPIO generating interrupts on the port where you connect the EXTI interrupt, then you may disable this IRQ in the NVIC, arm a timer for x µs, then re-enable teh EXIT interrupt in the NVIC when the timer expires; that is a bit more complex, but will cost less CPU cycles...

Bernard (Ac6)