Posted by MoeSzyslak on 2019-02-07 14:42

Normally it is not a great deal to implement a SPI interface with Nucleon STM32F767ZI. SPI functions are pre-implemented.

But in my case the slave doesn’t give the expected response as long the SPI frames have not special delimiters between some frames. See the picture in the attachment. The red encirceled MOSI pulses without SLK (clock) signals are need.

I used the code example from the CUBE “STM32Cube_FW_F7_V1.11.0” called “SPI_FullDuplex_ComIT”

I configured the SPI Handler as follows.

/*##-1- Configure the SPI peripheral #######################################*/
/* Set the SPI parameters */
SpiHandle.Instance = SPIx;
SpiHandle.Init.BaudRatePrescaler = SPI_BAUDRATEPRESCALER_16;
SpiHandle.Init.Direction = SPI_DIRECTION_2LINES;
SpiHandle.Init.CLKPhase = SPI_PHASE_2EDGE;
SpiHandle.Init.CLKPolarity = SPI_POLARITY_HIGH;
SpiHandle.Init.DataSize = SPI_DATASIZE_8BIT;
SpiHandle.Init.FirstBit = SPI_FIRSTBIT_MSB;
SpiHandle.Init.TIMode = SPI_TIMODE_DISABLE;
SpiHandle.Init.CRCCalculation = SPI_CRCCALCULATION_DISABLE;
SpiHandle.Init.CRCPolynomial = 7;
SpiHandle.Init.NSS = SPI_NSS_SOFT;

CPOL=1 and CPHA=1

But I have no idea how to realize the MOSI HIGH pulses between the SPI frames without a CLK signal. As long SPI is enabled I have no direct access to the MOSI Pin. So tried to disable SPI by means of HAL_SPI_DeInit( ...) in order to toggle the MOSI output pin from LOW to HIGH and back to LOW. Then I re-enabled the SPI function. But this method has the effect that the CLK signal which should remain on HIGH drops to LOW. The SPI re-initialisation causes then a rising CLK edge which is then interpreted as an extra bit at the receiver side.

What can I do to add a MOSI pulse between two frames without underlaying clock signal?

I already tried to implement a totally own SPI driver by toggeling the CLK signal with set and reset commands. But this is to slow for my application which requires a datarate of 6 Mbit/s.

SPI signal with delimeters