Error: jtag status contains invalid mode value - communication failure
This is log with “Connect under reset”:
Open On-Chip Debugger 0.10.0-dev-00010-g96aab7b (2018-07-13-06:43)
Licensed under GNU GPL v2
For bug reports, read
http://openocd.org/doc/doxygen/bugs.html
User : 13 2 command.c:544 command_print(): debug_level: 3
Debug: 14 2 configuration.c:42 add_script_search_dir(): adding /Users/sergeyzwezdin/Temp/black-pill-code/black-pill
Debug: 15 2 configuration.c:42 add_script_search_dir(): adding /Users/sergeyzwezdin/eclipse/cpp-photon/Eclipse.app/Contents/Eclipse/../../../../../.p2/pool/plugins/fr.ac6.mcu.debug_2.2.0.201807130628/resources/openocd/st_scripts
Debug: 16 2 options.c:181 add_default_dirs(): bindir=/src/staging/openocd/macos64/bin
Debug: 17 2 options.c:182 add_default_dirs(): pkgdatadir=/src/staging/openocd/macos64/share/openocd
Debug: 18 2 options.c:183 add_default_dirs(): exepath=/Users/sergeyzwezdin/.p2/pool/plugins/fr.ac6.mcu.externaltools.openocd.macos64_1.18.0.201807130628/tools/openocd/bin
Debug: 19 2 options.c:184 add_default_dirs(): bin2data=../share/openocd
Debug: 20 2 configuration.c:42 add_script_search_dir(): adding /Users/sergeyzwezdin/.openocd
Debug: 21 2 configuration.c:42 add_script_search_dir(): adding /Users/sergeyzwezdin/.p2/pool/plugins/fr.ac6.mcu.externaltools.openocd.macos64_1.18.0.201807130628/tools/openocd/bin/../share/openocd/site
Debug: 22 2 configuration.c:42 add_script_search_dir(): adding /Users/sergeyzwezdin/.p2/pool/plugins/fr.ac6.mcu.externaltools.openocd.macos64_1.18.0.201807130628/tools/openocd/bin/../share/openocd/scripts
Debug: 23 2 configuration.c:82 find_file(): found black-pill Run.cfg
Debug: 24 2 configuration.c:82 find_file(): found /Users/sergeyzwezdin/eclipse/cpp-photon/Eclipse.app/Contents/Eclipse/../../../../../.p2/pool/plugins/fr.ac6.mcu.debug_2.2.0.201807130628/resources/openocd/st_scripts/interface/stlink.cfg
Debug: 25 2 command.c:143 script_debug(): command - ocd_command ocd_command type ocd_interface hla
Debug: 26 2 command.c:143 script_debug(): command - interface ocd_interface hla
Debug: 28 2 command.c:364 register_command_handler(): registering ‘ocd_hla_device_desc’...
Debug: 29 2 command.c:364 register_command_handler(): registering ‘ocd_hla_serial’...
Debug: 30 2 command.c:364 register_command_handler(): registering ‘ocd_hla_layout’...
Debug: 31 2 command.c:364 register_command_handler(): registering ‘ocd_hla_vid_pid’...
Debug: 32 2 command.c:364 register_command_handler(): registering ‘ocd_hla_command’...
Debug: 33 2 command.c:143 script_debug(): command - ocd_command ocd_command type ocd_hla_layout stlink
Debug: 34 2 command.c:143 script_debug(): command - hla_layout ocd_hla_layout stlink
Debug: 36 2 hla_interface.c:239 hl_interface_handle_layout_command(): hl_interface_handle_layout_command
Debug: 37 2 command.c:143 script_debug(): command - ocd_command ocd_command type ocd_hla_device_desc ST-LINK
Debug: 38 2 command.c:143 script_debug(): command - hla_device_desc ocd_hla_device_desc ST-LINK
Debug: 40 2 hla_interface.c:213 hl_interface_handle_device_desc_command(): hl_interface_handle_device_desc_command
Debug: 41 2 command.c:143 script_debug(): command - ocd_command ocd_command type ocd_hla_vid_pid 0x0483 0x374b
Debug: 42 2 command.c:143 script_debug(): command - hla_vid_pid ocd_hla_vid_pid 0x0483 0x374b
Debug: 44 2 hla_interface.c:267 hl_interface_handle_vid_pid_command(): hl_interface_handle_vid_pid_command
Debug: 45 2 command.c:143 script_debug(): command - ocd_command ocd_command type ocd_transport select hla_swd
Debug: 46 2 command.c:143 script_debug(): command - ocd_transport ocd_transport select hla_swd
Debug: 47 2 hla_transport.c:191 hl_transport_select(): hl_transport_select
Debug: 48 2 command.c:364 register_command_handler(): registering ‘ocd_hla’...
Debug: 49 2 command.c:364 register_command_handler(): registering ‘ocd_jtag’...
Debug: 50 2 command.c:364 register_command_handler(): registering ‘ocd_jtag’...
Debug: 51 2 command.c:364 register_command_handler(): registering ‘ocd_jtag’...
Debug: 52 2 command.c:364 register_command_handler(): registering ‘ocd_jtag’...
Debug: 53 2 command.c:364 register_command_handler(): registering ‘ocd_jtag’...
Debug: 54 3 command.c:364 register_command_handler(): registering ‘ocd_jtag’...
Debug: 55 3 command.c:364 register_command_handler(): registering ‘ocd_jtag’...
Debug: 56 3 command.c:364 register_command_handler(): registering ‘ocd_jtag’...
Debug: 57 3 command.c:364 register_command_handler(): registering ‘ocd_jtag’...
Debug: 58 3 command.c:364 register_command_handler(): registering ‘ocd_jtag_ntrst_delay’...
Debug: 59 3 command.c:143 script_debug(): command - ocd_command ocd_command type ocd_reset_config srst_only srst_nogate connect_assert_srst
Debug: 60 3 command.c:143 script_debug(): command - reset_config ocd_reset_config srst_only srst_nogate connect_assert_srst
User : 62 3 command.c:544 command_print(): srst_only separate srst_nogate srst_open_drain connect_assert_srst
Debug: 63 3 configuration.c:82 find_file(): found /Users/sergeyzwezdin/eclipse/cpp-photon/Eclipse.app/Contents/Eclipse/../../../../../.p2/pool/plugins/fr.ac6.mcu.debug_2.2.0.201807130628/resources/openocd/st_scripts/target/stm32f4x.cfg
Debug: 64 3 configuration.c:82 find_file(): found /Users/sergeyzwezdin/eclipse/cpp-photon/Eclipse.app/Contents/Eclipse/../../../../../.p2/pool/plugins/fr.ac6.mcu.debug_2.2.0.201807130628/resources/openocd/st_scripts/target/swj-dp.tcl
Debug: 65 3 command.c:143 script_debug(): command - ocd_command ocd_command type ocd_transport select
Debug: 66 3 command.c:143 script_debug(): command - ocd_transport ocd_transport select
Debug: 67 3 configuration.c:82 find_file(): found /Users/sergeyzwezdin/eclipse/cpp-photon/Eclipse.app/Contents/Eclipse/../../../../../.p2/pool/plugins/fr.ac6.mcu.debug_2.2.0.201807130628/resources/openocd/st_scripts/mem_helper.tcl
Debug: 68 3 command.c:143 script_debug(): command - ocd_command ocd_command type ocd_add_usage_text mrw address
Debug: 69 3 command.c:143 script_debug(): command - add_usage_text ocd_add_usage_text mrw address
Debug: 71 3 command.c:1098 help_add_command(): added ‘mrw’ help text
Debug: 72 3 command.c:143 script_debug(): command - ocd_command ocd_command type ocd_add_help_text mrw Returns value of word in memory.
Debug: 73 3 command.c:143 script_debug(): command - add_help_text ocd_add_help_text mrw Returns value of word in memory.
Debug: 75 3 command.c:1111 help_add_command(): added ‘mrw’ help text
Debug: 76 3 command.c:143 script_debug(): command - ocd_command ocd_command type ocd_add_usage_text mrb address
Debug: 77 3 command.c:143 script_debug(): command - add_usage_text ocd_add_usage_text mrb address
Debug: 79 3 command.c:1098 help_add_command(): added ‘mrb’ help text
Debug: 80 3 command.c:143 script_debug(): command - ocd_command ocd_command type ocd_add_help_text mrb Returns value of byte in memory.
Debug: 81 3 command.c:143 script_debug(): command - add_help_text ocd_add_help_text mrb Returns value of byte in memory.
Debug: 83 3 command.c:1111 help_add_command(): added ‘mrb’ help text
Debug: 84 3 command.c:143 script_debug(): command - ocd_command ocd_command type ocd_add_usage_text mmw address setbits clearbits
Debug: 85 3 command.c:143 script_debug(): command - add_usage_text ocd_add_usage_text mmw address setbits clearbits
Debug: 87 3 command.c:1098 help_add_command(): added ‘mmw’ help text
Debug: 88 3 command.c:143 script_debug(): command - ocd_command ocd_command type ocd_add_help_text mmw Modify word in memory. new_val = (old_val & ~clearbits) | setbits;
Debug: 89 3 command.c:143 script_debug(): command - add_help_text ocd_add_help_text mmw Modify word in memory. new_val = (old_val & ~clearbits) | setbits;
Debug: 91 3 command.c:1111 help_add_command(): added ‘mmw’ help text
Debug: 92 3 command.c:143 script_debug(): command - ocd_command ocd_command type ocd_transport select
Debug: 93 3 command.c:143 script_debug(): command - ocd_transport ocd_transport select
Debug: 94 3 command.c:143 script_debug(): command - ocd_command ocd_command type ocd_transport select
Debug: 95 3 command.c:143 script_debug(): command - ocd_transport ocd_transport select
Debug: 96 3 command.c:143 script_debug(): command - ocd_command ocd_command type ocd_transport select
Debug: 97 3 command.c:143 script_debug(): command - ocd_transport ocd_transport select
Debug: 98 3 command.c:143 script_debug(): command - ocd_command ocd_command type ocd_transport select
Debug: 99 3 command.c:143 script_debug(): command - ocd_transport ocd_transport select
Debug: 100 3 command.c:143 script_debug(): command - ocd_command ocd_command type ocd_hla newtap STM32F405RGTx cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id 0x2ba01477
Debug: 101 3 command.c:143 script_debug(): command - ocd_hla ocd_hla newtap STM32F405RGTx cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id 0x2ba01477
Debug: 102 3 hla_tcl.c:116 jim_hl_newtap_cmd(): Creating New Tap, Chip: STM32F405RGTx, Tap: cpu, Dotted: STM32F405RGTx.cpu, 8 params
Debug: 103 3 hla_tcl.c:126 jim_hl_newtap_cmd(): Processing option: -irlen
Debug: 104 3 hla_tcl.c:126 jim_hl_newtap_cmd(): Processing option: -ircapture
Debug: 105 3 hla_tcl.c:126 jim_hl_newtap_cmd(): Processing option: -irmask
Debug: 106 3 hla_tcl.c:126 jim_hl_newtap_cmd(): Processing option: -expected-id
Debug: 107 3 core.c:1304 jtag_tap_init(): Created Tap: STM32F405RGTx.cpu @ abs position 0, irlen 0, capture: 0x0 mask: 0x0
Debug: 108 4 command.c:143 script_debug(): command - ocd_command ocd_command type ocd_transport select
Debug: 109 4 command.c:143 script_debug(): command - ocd_transport ocd_transport select
Debug: 110 4 command.c:143 script_debug(): command - ocd_command ocd_command type ocd_target create STM32F405RGTx.cpu cortex_m -endian little -chain-position STM32F405RGTx.cpu
Debug: 111 4 command.c:143 script_debug(): command - ocd_target ocd_target create STM32F405RGTx.cpu cortex_m -endian little -chain-position STM32F405RGTx.cpu
Info : 112 4 target.c:5471 target_create(): The selected transport took over low-level target control. The results might differ compared to plain JTAG/SWD
Debug: 113 4 target.c:1920 target_free_all_working_areas_restore(): freeing all working areas
Debug: 114 4 command.c:364 register_command_handler(): registering ‘ocd_arm’...
Debug: 115 4 command.c:364 register_command_handler(): registering ‘ocd_arm’...
Debug: 116 4 command.c:364 register_command_handler(): registering ‘ocd_arm’...
Debug: 117 4 command.c:364 register_command_handler(): registering ‘ocd_arm’...
Debug: 118 4 command.c:364 register_command_handler(): registering ‘ocd_arm’...
Debug: 119 4 command.c:364 register_command_handler(): registering ‘ocd_arm’...
Debug: 120 4 command.c:364 register_command_handler(): registering ‘ocd_arm’...
Debug: 121 4 command.c:364 register_command_handler(): registering ‘ocd_tpiu’...
Debug: 122 4 command.c:364 register_command_handler(): registering ‘ocd_itm’...
Debug: 123 4 command.c:364 register_command_handler(): registering ‘ocd_itm’...
Debug: 124 4 hla_target.c:351 adapter_target_create(): adapter_target_create
Debug: 125 4 hla_target.c:322 adapter_init_arch_info(): adapter_init_arch_info
Debug: 126 4 command.c:364 register_command_handler(): registering ‘ocd_STM32F405RGTx.cpu’...
Debug: 127 4 command.c:364 register_command_handler(): registering ‘ocd_STM32F405RGTx.cpu’...
Debug: 128 4 command.c:364 register_command_handler(): registering ‘ocd_STM32F405RGTx.cpu’...
Debug: 129 4 command.c:364 register_command_handler(): registering ‘ocd_STM32F405RGTx.cpu’...
Debug: 130 4 command.c:364 register_command_handler(): registering ‘ocd_STM32F405RGTx.cpu’...
Debug: 131 4 command.c:364 register_command_handler(): registering ‘ocd_STM32F405RGTx.cpu’...
Debug: 132 4 command.c:364 register_command_handler(): registering ‘ocd_STM32F405RGTx.cpu’...
Debug: 133 4 command.c:364 register_command_handler(): registering ‘ocd_STM32F405RGTx.cpu’...
Debug: 134 4 command.c:364 register_command_handler(): registering ‘ocd_STM32F405RGTx.cpu’...
Debug: 135 4 command.c:364 register_command_handler(): registering ‘ocd_STM32F405RGTx.cpu’...
Debug: 136 4 command.c:364 register_command_handler(): registering ‘ocd_STM32F405RGTx.cpu’...
Debug: 137 4 command.c:364 register_command_handler(): registering ‘ocd_STM32F405RGTx.cpu’...
Debug: 138 4 command.c:364 register_command_handler(): registering ‘ocd_STM32F405RGTx.cpu’...
Debug: 139 4 command.c:364 register_command_handler(): registering ‘ocd_STM32F405RGTx.cpu’...
Debug: 140 4 command.c:364 register_command_handler(): registering ‘ocd_STM32F405RGTx.cpu’...
Debug: 141 4 command.c:364 register_command_handler(): registering ‘ocd_STM32F405RGTx.cpu’...
Debug: 142 4 command.c:364 register_command_handler(): registering ‘ocd_STM32F405RGTx.cpu’...
Debug: 143 4 command.c:364 register_command_handler(): registering ‘ocd_STM32F405RGTx.cpu’...
Debug: 144 4 command.c:364 register_command_handler(): registering ‘ocd_STM32F405RGTx.cpu’...
Debug: 145 4 command.c:364 register_command_handler(): registering ‘ocd_STM32F405RGTx.cpu’...
Debug: 146 4 command.c:364 register_command_handler(): registering ‘ocd_STM32F405RGTx.cpu’...
Debug: 147 4 command.c:364 register_command_handler(): registering ‘ocd_STM32F405RGTx.cpu’...
Debug: 148 4 command.c:364 register_command_handler(): registering ‘ocd_STM32F405RGTx.cpu’...
Debug: 149 4 command.c:364 register_command_handler(): registering ‘ocd_STM32F405RGTx.cpu’...
Debug: 150 4 command.c:364 register_command_handler(): registering ‘ocd_STM32F405RGTx.cpu’...
Debug: 151 4 command.c:364 register_command_handler(): registering ‘ocd_STM32F405RGTx.cpu’...
Debug: 152 4 command.c:364 register_command_handler(): registering ‘ocd_STM32F405RGTx.cpu’...
Debug: 153 4 command.c:364 register_command_handler(): registering ‘ocd_STM32F405RGTx.cpu’...
Debug: 154 4 command.c:364 register_command_handler(): registering ‘ocd_STM32F405RGTx.cpu’...
Debug: 155 4 command.c:364 register_command_handler(): registering ‘ocd_STM32F405RGTx.cpu’...
Debug: 156 4 command.c:364 register_command_handler(): registering ‘ocd_STM32F405RGTx.cpu’...
Debug: 157 4 command.c:364 register_command_handler(): registering ‘ocd_STM32F405RGTx.cpu’...
Debug: 158 4 command.c:364 register_command_handler(): registering ‘ocd_STM32F405RGTx.cpu’...
Debug: 159 4 command.c:364 register_command_handler(): registering ‘ocd_STM32F405RGTx.cpu’...
Debug: 160 4 command.c:143 script_debug(): command - ocd_command ocd_command type ocd_STM32F405RGTx.cpu configure -work-area-phys 0x20000000 -work-area-size 0x8000 -work-area-backup 0
Debug: 161 4 command.c:143 script_debug(): command - ocd_STM32F405RGTx.cpu ocd_STM32F405RGTx.cpu configure -work-area-phys 0x20000000 -work-area-size 0x8000 -work-area-backup 0
Debug: 162 4 target.c:1920 target_free_all_working_areas_restore(): freeing all working areas
Debug: 163 4 target.c:1920 target_free_all_working_areas_restore(): freeing all working areas
Debug: 164 4 target.c:1920 target_free_all_working_areas_restore(): freeing all working areas
Debug: 165 4 command.c:143 script_debug(): command - ocd_command ocd_command type ocd_flash bank STM32F405RGTx.flash stm32f2x 0 0 0 0 STM32F405RGTx.cpu
Debug: 166 4 command.c:143 script_debug(): command - ocd_flash ocd_flash bank STM32F405RGTx.flash stm32f2x 0 0 0 0 STM32F405RGTx.cpu
Debug: 168 4 command.c:364 register_command_handler(): registering ‘ocd_stm32f2x’...
Debug: 169 4 command.c:364 register_command_handler(): registering ‘ocd_stm32f2x’...
Debug: 170 4 command.c:364 register_command_handler(): registering ‘ocd_stm32f2x’...
Debug: 171 4 tcl.c:1131 handle_flash_bank_command(): ‘stm32f2x’ driver usage field missing
Debug: 172 4 command.c:143 script_debug(): command - ocd_command ocd_command type ocd_adapter_nsrst_delay 100
Debug: 173 4 command.c:143 script_debug(): command - adapter_nsrst_delay ocd_adapter_nsrst_delay 100
User : 175 4 command.c:544 command_print(): adapter_nsrst_delay: 100
Debug: 176 4 command.c:143 script_debug(): command - ocd_command ocd_command type ocd_transport select
Debug: 177 4 command.c:143 script_debug(): command - ocd_transport ocd_transport select
Debug: 178 4 command.c:143 script_debug(): command - ocd_command ocd_command type ocd_adapter_khz 1800
Debug: 179 4 command.c:143 script_debug(): command - adapter_khz ocd_adapter_khz 1800
Debug: 181 4 core.c:1631 jtag_config_khz(): handle jtag khz
Debug: 182 4 core.c:1598 adapter_khz_to_speed(): convert khz to interface specific speed value
Debug: 183 4 core.c:1598 adapter_khz_to_speed(): convert khz to interface specific speed value
User : 184 4 command.c:544 command_print(): adapter speed: 1800 kHz
Debug: 185 4 command.c:143 script_debug(): command - ocd_command ocd_command type ocd_transport select
Debug: 186 4 command.c:143 script_debug(): command - ocd_transport ocd_transport select
Debug: 187 4 command.c:143 script_debug(): command - ocd_command ocd_command type ocd_STM32F405RGTx.cpu configure -event examine-end
global ENABLE_LOW_POWER
global STOP_WATCHDOG
if { expr ($ENABLE_LOW_POWER == 1) } {
# Enable debug during low power modes (uses more power)
# DBGMCU_CR |= DBG_STANDBY | DBG_STOP | DBG_SLEEP
mmw 0xE0042004 0x00000007 0
}
if { expr ($ENABLE_LOW_POWER == 0) } {
# Disable debug during low power modes
# DBGMCU_CR |= ~(DBG_STANDBY | DBG_STOP | DBG_SLEEP)
mmw 0xE0042004 0 0x00000007
}
if { expr ($STOP_WATCHDOG == 1) } {
# Stop watchdog counters during halt
# DBGMCU_APB1_FZ |= DBG_IWDG_STOP | DBG_WWDG_STOP
mmw 0xE0042008 0x00001800 0
}
if { expr ($STOP_WATCHDOG == 0) } {
# Don’t stop watchdog counters during halt
# DBGMCU_APB1_FZ |= ~(DBG_IWDG_STOP | DBG_WWDG_STOP)
mmw 0xE0042008 0 0x00001800
}
Debug: 188 4 command.c:143 script_debug(): command - ocd_STM32F405RGTx.cpu ocd_STM32F405RGTx.cpu configure -event examine-end
global ENABLE_LOW_POWER
global STOP_WATCHDOG
if { expr ($ENABLE_LOW_POWER == 1) } {
# Enable debug during low power modes (uses more power)
# DBGMCU_CR |= DBG_STANDBY | DBG_STOP | DBG_SLEEP
mmw 0xE0042004 0x00000007 0
}
if { expr ($ENABLE_LOW_POWER == 0) } {
# Disable debug during low power modes
# DBGMCU_CR |= ~(DBG_STANDBY | DBG_STOP | DBG_SLEEP)
mmw 0xE0042004 0 0x00000007
}
if { expr ($STOP_WATCHDOG == 1) } {
# Stop watchdog counters during halt
# DBGMCU_APB1_FZ |= DBG_IWDG_STOP | DBG_WWDG_STOP
mmw 0xE0042008 0x00001800 0
}
if { expr ($STOP_WATCHDOG == 0) } {
# Don’t stop watchdog counters during halt
# DBGMCU_APB1_FZ |= ~(DBG_IWDG_STOP | DBG_WWDG_STOP)
mmw 0xE0042008 0 0x00001800
}
Debug: 189 4 command.c:143 script_debug(): command - ocd_command ocd_command type ocd_STM32F405RGTx.cpu configure -event trace-config
# Set TRACE_IOEN; TRACE_MODE is set to async; when using sync
# change this value accordingly to configure trace pins
# assignment
mmw 0xE0042004 0x00000020 0
Debug: 190 4 command.c:143 script_debug(): command - ocd_STM32F405RGTx.cpu ocd_STM32F405RGTx.cpu configure -event trace-config
# Set TRACE_IOEN; TRACE_MODE is set to async; when using sync
# change this value accordingly to configure trace pins
# assignment
mmw 0xE0042004 0x00000020 0
Debug: 191 4 command.c:143 script_debug(): command - ocd_command ocd_command type ocd_STM32F405RGTx.cpu configure -event reset-start
if {using_jtag} {
adapter_khz 1125
} else {
adapter_khz 1800
}
Debug: 192 5 command.c:143 script_debug(): command - ocd_STM32F405RGTx.cpu ocd_STM32F405RGTx.cpu configure -event reset-start
if {using_jtag} {
adapter_khz 1125
} else {
adapter_khz 1800
}
Debug: 193 5 command.c:143 script_debug(): command - ocd_command ocd_command type ocd_STM32F405RGTx.cpu configure -event reset-init
global _CLOCK_FREQ
echo “configuring PLL”
# Configure PLL to boost clock to HSI x 8 (64 MHz)
mww 0x40023800 0x00008a81 ;# RCC_CR = HSICALbogus = 138 | HSITRIM16 | HSION (reset value)
mww 0x40023808 0x00000000 ;# RCC_CFGR = (all = div1), select HSI as main clock source. (reset value)
mww 0x4002380c 0x00000000 ;# RCC_CIR = 0, all off. (reset value)
mww 0x40023804 0x24403010 ;# RCC_PLLCFGR = PLLQdiv4 | PLLSRCHSI | PLLPdiv2 | PLLNmul192 | PLLMdiv16 (reset value)
mww 0x40023c00 0x00000103 ;# FLASH_ACR = PRFTEN | LATENCY2 (we’ll run at 84 MHz, see section 3.5.1, table 10 and table 11)
mww 0x40023800 0x01008a81 ;# RCC_CR = PLLON | HSICALbogus = 138 | HSITRIM16 | HSION (enable PLL)
sleep 10 ;# Wait for PLL to lock
mww 0x40023808 0x00000002 ;# RCC_CFGR = (all = div1), select PLL as main clock source. (we should now run at 84 MHz)
adapter_khz $_CLOCK_FREQ
Debug: 194 5 command.c:143 script_debug(): command - ocd_STM32F405RGTx.cpu ocd_STM32F405RGTx.cpu configure -event reset-init
global _CLOCK_FREQ
echo “configuring PLL”
# Configure PLL to boost clock to HSI x 8 (64 MHz)
mww 0x40023800 0x00008a81 ;# RCC_CR = HSICALbogus = 138 | HSITRIM16 | HSION (reset value)
mww 0x40023808 0x00000000 ;# RCC_CFGR = (all = div1), select HSI as main clock source. (reset value)
mww 0x4002380c 0x00000000 ;# RCC_CIR = 0, all off. (reset value)
mww 0x40023804 0x24403010 ;# RCC_PLLCFGR = PLLQdiv4 | PLLSRCHSI | PLLPdiv2 | PLLNmul192 | PLLMdiv16 (reset value)
mww 0x40023c00 0x00000103 ;# FLASH_ACR = PRFTEN | LATENCY2 (we’ll run at 84 MHz, see section 3.5.1, table 10 and table 11)
mww 0x40023800 0x01008a81 ;# RCC_CR = PLLON | HSICALbogus = 138 | HSITRIM16 | HSION (enable PLL)
sleep 10 ;# Wait for PLL to lock
mww 0x40023808 0x00000002 ;# RCC_CFGR = (all = div1), select PLL as main clock source. (we should now run at 84 MHz)
adapter_khz $_CLOCK_FREQ
Debug: 195 5 command.c:143 script_debug(): command - ocd_command ocd_command type ocd_STM32F405RGTx.cpu configure -event gdb-attach
global CONNECT_UNDER_RESET
# Needed to be able to use the connect_assert_srst in reset_config
# otherwise, wrong value when reading device flash size register
if { expr ($CONNECT_UNDER_RESET == 1) } {
reset init
}
Debug: 196 5 command.c:143 script_debug(): command - ocd_STM32F405RGTx.cpu ocd_STM32F405RGTx.cpu configure -event gdb-attach
global CONNECT_UNDER_RESET
# Needed to be able to use the connect_assert_srst in reset_config
# otherwise, wrong value when reading device flash size register
if { expr ($CONNECT_UNDER_RESET == 1) } {
reset init
}
Debug: 197 5 command.c:143 script_debug(): command - ocd_command ocd_command type ocd_STM32F405RGTx.cpu configure -event gdb-detach
# to close connection if debug mode entered
shutdown
Debug: 198 5 command.c:143 script_debug(): command - ocd_STM32F405RGTx.cpu ocd_STM32F405RGTx.cpu configure -event gdb-detach
# to close connection if debug mode entered
shutdown
Debug: 199 5 command.c:143 script_debug(): command - ocd_command ocd_command type ocd_init
Debug: 200 5 command.c:143 script_debug(): command - init ocd_init
Debug: 202 5 command.c:143 script_debug(): command - ocd_command ocd_command type ocd_target init
Debug: 203 5 command.c:143 script_debug(): command - ocd_target ocd_target init
Debug: 205 5 command.c:143 script_debug(): command - ocd_command ocd_command type ocd_target names
Debug: 206 5 command.c:143 script_debug(): command - ocd_target ocd_target names
Debug: 207 5 command.c:143 script_debug(): command - ocd_command ocd_command type ocd_STM32F405RGTx.cpu cget -event gdb-flash-erase-start
Debug: 208 5 command.c:143 script_debug(): command - ocd_STM32F405RGTx.cpu ocd_STM32F405RGTx.cpu cget -event gdb-flash-erase-start
Debug: 209 5 command.c:143 script_debug(): command - ocd_command ocd_command type ocd_STM32F405RGTx.cpu configure -event gdb-flash-erase-start reset init
Debug: 210 5 command.c:143 script_debug(): command - ocd_STM32F405RGTx.cpu ocd_STM32F405RGTx.cpu configure -event gdb-flash-erase-start reset init
Debug: 211 5 command.c:143 script_debug(): command - ocd_command ocd_command type ocd_STM32F405RGTx.cpu cget -event gdb-flash-write-end
Debug: 212 5 command.c:143 script_debug(): command - ocd_STM32F405RGTx.cpu ocd_STM32F405RGTx.cpu cget -event gdb-flash-write-end
Debug: 213 5 command.c:143 script_debug(): command - ocd_command ocd_command type ocd_STM32F405RGTx.cpu configure -event gdb-flash-write-end reset halt
Debug: 214 5 command.c:143 script_debug(): command - ocd_STM32F405RGTx.cpu ocd_STM32F405RGTx.cpu configure -event gdb-flash-write-end reset halt
Debug: 215 5 target.c:1329 handle_target_init_command(): Initializing targets...
Debug: 216 5 hla_target.c:341 adapter_init_target(): adapter_init_target
Debug: 217 5 command.c:364 register_command_handler(): registering ‘ocd_target_request’...
Debug: 218 5 command.c:364 register_command_handler(): registering ‘ocd_trace’...
Debug: 219 5 command.c:364 register_command_handler(): registering ‘ocd_trace’...
Debug: 220 5 command.c:364 register_command_handler(): registering ‘ocd_fast_load_image’...
Debug: 221 5 command.c:364 register_command_handler(): registering ‘ocd_fast_load’...
Debug: 222 5 command.c:364 register_command_handler(): registering ‘ocd_profile’...
Debug: 223 5 command.c:364 register_command_handler(): registering ‘ocd_virt2phys’...
Debug: 224 5 command.c:364 register_command_handler(): registering ‘ocd_reg’...
Debug: 225 5 command.c:364 register_command_handler(): registering ‘ocd_poll’...
Debug: 226 5 command.c:364 register_command_handler(): registering ‘ocd_wait_halt’...
Debug: 227 5 command.c:364 register_command_handler(): registering ‘ocd_halt’...
Debug: 228 5 command.c:364 register_command_handler(): registering ‘ocd_resume’...
Debug: 229 5 command.c:364 register_command_handler(): registering ‘ocd_reset’...
Debug: 230 5 command.c:364 register_command_handler(): registering ‘ocd_soft_reset_halt’...
Debug: 231 5 command.c:364 register_command_handler(): registering ‘ocd_step’...
Debug: 232 5 command.c:364 register_command_handler(): registering ‘ocd_mdd’...
Debug: 233 5 command.c:364 register_command_handler(): registering ‘ocd_mdw’...
Debug: 234 5 command.c:364 register_command_handler(): registering ‘ocd_mdh’...
Debug: 235 5 command.c:364 register_command_handler(): registering ‘ocd_mdb’...
Debug: 236 5 command.c:364 register_command_handler(): registering ‘ocd_mwd’...
Debug: 237 5 command.c:364 register_command_handler(): registering ‘ocd_mww’...
Debug: 238 5 command.c:364 register_command_handler(): registering ‘ocd_mwh’...
Debug: 239 5 command.c:364 register_command_handler(): registering ‘ocd_mwb’...
Debug: 240 5 command.c:364 register_command_handler(): registering ‘ocd_bp’...
Debug: 241 5 command.c:364 register_command_handler(): registering ‘ocd_rbp’...
Debug: 242 5 command.c:364 register_command_handler(): registering ‘ocd_wp’...
Debug: 243 5 command.c:364 register_command_handler(): registering ‘ocd_rwp’...
Debug: 244 5 command.c:364 register_command_handler(): registering ‘ocd_load_image’...
Debug: 245 5 command.c:364 register_command_handler(): registering ‘ocd_dump_image’...
Debug: 246 5 command.c:364 register_command_handler(): registering ‘ocd_verify_image_checksum’...
Debug: 247 5 command.c:364 register_command_handler(): registering ‘ocd_verify_image’...
Debug: 248 5 command.c:364 register_command_handler(): registering ‘ocd_test_image’...
Debug: 249 5 command.c:364 register_command_handler(): registering ‘ocd_reset_nag’...
Debug: 250 5 command.c:364 register_command_handler(): registering ‘ocd_ps’...
Debug: 251 5 command.c:364 register_command_handler(): registering ‘ocd_test_mem_access’...
Debug: 252 5 hla_interface.c:109 hl_interface_init(): hl_interface_init
Debug: 253 5 hla_layout.c:89 hl_layout_init(): hl_layout_init
Debug: 254 5 core.c:1598 adapter_khz_to_speed(): convert khz to interface specific speed value
Debug: 255 5 core.c:1601 adapter_khz_to_speed(): have interface set up
Debug: 256 5 core.c:1598 adapter_khz_to_speed(): convert khz to interface specific speed value
Debug: 257 5 core.c:1601 adapter_khz_to_speed(): have interface set up
Info : 258 5 core.c:1386 adapter_init(): clock speed 1800 kHz
Debug: 259 5 openocd.c:140 handle_init_command(): Debug Adapter init complete
Debug: 260 5 command.c:143 script_debug(): command - ocd_command ocd_command type ocd_transport init
Debug: 261 6 command.c:143 script_debug(): command - ocd_transport ocd_transport init
Debug: 263 6 transport.c:239 handle_transport_init(): handle_transport_init
Debug: 264 6 hla_transport.c:152 hl_transport_init(): hl_transport_init
Debug: 265 6 hla_transport.c:169 hl_transport_init(): current transport hla_swd
Debug: 266 6 hla_interface.c:42 hl_interface_open(): hl_interface_open
Debug: 267 6 hla_layout.c:40 hl_layout_open(): hl_layout_open
Debug: 268 6 stlink_usb.c:2070 stlink_usb_open(): stlink_usb_open
Debug: 269 6 stlink_usb.c:2086 stlink_usb_open(): transport: 1 vid: 0x0483 pid: 0x374b serial:
Info : 270 10 stlink_usb.c:709 stlink_usb_version(): STLINK v2 JTAG v28 API v2 SWIM v7 VID 0x0483 PID 0x3748
Info : 271 10 stlink_usb.c:2184 stlink_usb_open(): vid/pid are not identical: 0x0483/0x374B 0x0483/0x3748
Info : 272 10 stlink_usb.c:2211 stlink_usb_open(): using stlink api v2
Debug: 273 10 stlink_usb.c:934 stlink_exit_mode(): MODE: 0x01
Debug: 274 10 stlink_usb.c:987 stlink_usb_init_mode(): MODE: 0x01
Info : 275 11 stlink_usb.c:742 stlink_usb_check_voltage(): Target voltage: 3.260318
Debug: 276 12 stlink_usb.c:1036 stlink_usb_init_mode(): MODE: 0x02
Debug: 277 12 stlink_usb.c:2248 stlink_usb_open(): Supported SWD clock speeds are:
Debug: 278 12 stlink_usb.c:2252 stlink_usb_open(): 4000 kHz
Debug: 279 12 stlink_usb.c:2252 stlink_usb_open(): 1800 kHz
Debug: 280 12 stlink_usb.c:2252 stlink_usb_open(): 1200 kHz
Debug: 281 12 stlink_usb.c:2252 stlink_usb_open(): 950 kHz
Debug: 282 12 stlink_usb.c:2252 stlink_usb_open(): 480 kHz
Debug: 283 12 stlink_usb.c:2252 stlink_usb_open(): 240 kHz
Debug: 284 12 stlink_usb.c:2252 stlink_usb_open(): 125 kHz
Debug: 285 12 stlink_usb.c:2252 stlink_usb_open(): 100 kHz
Debug: 286 12 stlink_usb.c:2252 stlink_usb_open(): 50 kHz
Debug: 287 12 stlink_usb.c:2252 stlink_usb_open(): 25 kHz
Debug: 288 12 stlink_usb.c:2252 stlink_usb_open(): 15 kHz
Debug: 289 12 stlink_usb.c:2252 stlink_usb_open(): 5 kHz
Info : 290 13 stlink_usb.c:2009 stlink_speed_v2(): Stlink adapter speed set to 1800 kHz
Debug: 291 13 stlink_usb.c:2281 stlink_usb_open(): Using TAR autoincrement: 4096
Debug: 292 13 hla_interface.c:127 hl_interface_execute_queue(): hl_interface_execute_queue: ignored
Debug: 293 13 core.c:725 jtag_add_reset(): SRST line asserted
Debug: 294 13 core.c:753 jtag_add_reset(): TRST line released
Debug: 295 13 core.c:327 jtag_call_event_callbacks(): jtag event: TAP reset
Debug: 296 13 hla_interface.c:67 hl_interface_init_target(): hl_interface_init_target
Debug: 297 14 stlink_usb.c:1061 stlink_usb_idcode(): IDCODE: 0x2BA01477
Debug: 298 14 openocd.c:153 handle_init_command(): Examining targets...
Debug: 299 14 target.c:1522 target_call_event_callbacks(): target event 21 (examine-start)
Debug: 300 14 hla_target.c:751 adapter_read_memory(): adapter_read_memory 0xe000ed00 4 1
Debug: 301 14 target.c:2262 target_read_u32(): address: 0xe000ed00, value: 0x410fc241
Debug: 302 14 cortex_m.c:1921 cortex_m_examine(): Cortex-M4 r0p1 processor detected
Debug: 303 14 cortex_m.c:1929 cortex_m_examine(): cpuid: 0x410fc241
Debug: 304 14 hla_target.c:751 adapter_read_memory(): adapter_read_memory 0xe000ef40 4 1
Debug: 305 15 target.c:2262 target_read_u32(): address: 0xe000ef40, value: 0x10110021
Debug: 306 15 hla_target.c:751 adapter_read_memory(): adapter_read_memory 0xe000ef44 4 1
Debug: 307 15 target.c:2262 target_read_u32(): address: 0xe000ef44, value: 0x11000011
Debug: 308 15 cortex_m.c:1937 cortex_m_examine(): Cortex-M4 floating point feature FPv4_SP found
Debug: 309 15 target.c:2350 target_write_u32(): address: 0xe000edfc, value: 0x01000000
Debug: 310 15 hla_target.c:766 adapter_write_memory(): adapter_write_memory 0xe000edfc 4 1
Debug: 311 16 hla_target.c:751 adapter_read_memory(): adapter_read_memory 0xe0002000 4 1
Debug: 312 16 target.c:2262 target_read_u32(): address: 0xe0002000, value: 0x00000260
Debug: 313 16 target.c:2350 target_write_u32(): address: 0xe0002008, value: 0x00000000
Debug: 314 16 hla_target.c:766 adapter_write_memory(): adapter_write_memory 0xe0002008 4 1
Debug: 315 17 target.c:2350 target_write_u32(): address: 0xe000200c, value: 0x00000000
Debug: 316 17 hla_target.c:766 adapter_write_memory(): adapter_write_memory 0xe000200c 4 1
Debug: 317 18 target.c:2350 target_write_u32(): address: 0xe0002010, value: 0x00000000
Debug: 318 18 hla_target.c:766 adapter_write_memory(): adapter_write_memory 0xe0002010 4 1
Debug: 319 18 target.c:2350 target_write_u32(): address: 0xe0002014, value: 0x00000000
Debug: 320 18 hla_target.c:766 adapter_write_memory(): adapter_write_memory 0xe0002014 4 1
Debug: 321 19 target.c:2350 target_write_u32(): address: 0xe0002018, value: 0x00000000
Debug: 322 19 hla_target.c:766 adapter_write_memory(): adapter_write_memory 0xe0002018 4 1
Debug: 323 19 target.c:2350 target_write_u32(): address: 0xe000201c, value: 0x00000000
Debug: 324 19 hla_target.c:766 adapter_write_memory(): adapter_write_memory 0xe000201c 4 1
Debug: 325 20 target.c:2350 target_write_u32(): address: 0xe0002020, value: 0x00000000
Debug: 326 20 hla_target.c:766 adapter_write_memory(): adapter_write_memory 0xe0002020 4 1
Debug: 327 20 target.c:2350 target_write_u32(): address: 0xe0002024, value: 0x00000000
Debug: 328 20 hla_target.c:766 adapter_write_memory(): adapter_write_memory 0xe0002024 4 1
Debug: 329 21 cortex_m.c:2019 cortex_m_examine(): FPB fpcr 0x260, numcode 6, numlit 2
Debug: 330 21 hla_target.c:751 adapter_read_memory(): adapter_read_memory 0xe0001000 4 1
Debug: 331 21 target.c:2262 target_read_u32(): address: 0xe0001000, value: 0x40000000
Debug: 332 21 target.c:2350 target_write_u32(): address: 0xe0001028, value: 0x00000000
Debug: 333 21 hla_target.c:766 adapter_write_memory(): adapter_write_memory 0xe0001028 4 1
Debug: 334 22 target.c:2350 target_write_u32(): address: 0xe0001038, value: 0x00000000
Debug: 335 22 hla_target.c:766 adapter_write_memory(): adapter_write_memory 0xe0001038 4 1
Debug: 336 22 target.c:2350 target_write_u32(): address: 0xe0001048, value: 0x00000000
Debug: 337 22 hla_target.c:766 adapter_write_memory(): adapter_write_memory 0xe0001048 4 1
Debug: 338 23 target.c:2350 target_write_u32(): address: 0xe0001058, value: 0x00000000
Debug: 339 23 hla_target.c:766 adapter_write_memory(): adapter_write_memory 0xe0001058 4 1
Debug: 340 23 cortex_m.c:1831 cortex_m_dwt_setup(): DWT dwtcr 0x40000000, comp 4, watch/trigger
Info : 341 23 cortex_m.c:2029 cortex_m_examine(): STM32F405RGTx.cpu: hardware has 6 breakpoints, 4 watchpoints
Debug: 342 23 target.c:1522 target_call_event_callbacks(): target event 22 (examine-end)
Debug: 343 23 target.c:4429 target_handle_event(): target: (0) STM32F405RGTx.cpu (hla_target) event: 22 (examine-end) action:
global ENABLE_LOW_POWER
global STOP_WATCHDOG
if { expr ($ENABLE_LOW_POWER == 1) } {
# Enable debug during low power modes (uses more power)
# DBGMCU_CR |= DBG_STANDBY | DBG_STOP | DBG_SLEEP
mmw 0xE0042004 0x00000007 0
}
if { expr ($ENABLE_LOW_POWER == 0) } {
# Disable debug during low power modes
# DBGMCU_CR |= ~(DBG_STANDBY | DBG_STOP | DBG_SLEEP)
mmw 0xE0042004 0 0x00000007
}
if { expr ($STOP_WATCHDOG == 1) } {
# Stop watchdog counters during halt
# DBGMCU_APB1_FZ |= DBG_IWDG_STOP | DBG_WWDG_STOP
mmw 0xE0042008 0x00001800 0
}
if { expr ($STOP_WATCHDOG == 0) } {
# Don’t stop watchdog counters during halt
# DBGMCU_APB1_FZ |= ~(DBG_IWDG_STOP | DBG_WWDG_STOP)
mmw 0xE0042008 0 0x00001800
}
Debug: 344 23 hla_target.c:751 adapter_read_memory(): adapter_read_memory 0xe0042004 4 1
Debug: 345 24 command.c:143 script_debug(): command - ocd_command ocd_command type ocd_mww 0xE0042004 7
Debug: 346 24 command.c:143 script_debug(): command - mww ocd_mww 0xE0042004 7
Debug: 348 24 hla_target.c:766 adapter_write_memory(): adapter_write_memory 0xe0042004 4 1
Debug: 349 25 hla_target.c:751 adapter_read_memory(): adapter_read_memory 0xe0042008 4 1
Debug: 350 26 command.c:143 script_debug(): command - ocd_command ocd_command type ocd_mww 0xE0042008 6144
Debug: 351 26 command.c:143 script_debug(): command - mww ocd_mww 0xE0042008 6144
Debug: 353 26 hla_target.c:766 adapter_write_memory(): adapter_write_memory 0xe0042008 4 1
Debug: 354 27 command.c:143 script_debug(): command - ocd_command ocd_command type ocd_flash init
Debug: 355 27 command.c:143 script_debug(): command - ocd_flash ocd_flash init
Debug: 357 27 tcl.c:1197 handle_flash_init_command(): Initializing flash devices...
Debug: 358 27 command.c:364 register_command_handler(): registering ‘ocd_flash’...
Debug: 359 27 command.c:364 register_command_handler(): registering ‘ocd_flash’...
Debug: 360 27 command.c:364 register_command_handler(): registering ‘ocd_flash’...
Debug: 361 27 command.c:364 register_command_handler(): registering ‘ocd_flash’...
Debug: 362 27 command.c:364 register_command_handler(): registering ‘ocd_flash’...
Debug: 363 27 command.c:364 register_command_handler(): registering ‘ocd_flash’...
Debug: 364 27 command.c:364 register_command_handler(): registering ‘ocd_flash’...
Debug: 365 27 command.c:364 register_command_handler(): registering ‘ocd_flash’...
Debug: 366 27 command.c:364 register_command_handler(): registering ‘ocd_flash’...
Debug: 367 27 command.c:364 register_command_handler(): registering ‘ocd_flash’...
Debug: 368 27 command.c:364 register_command_handler(): registering ‘ocd_flash’...
Debug: 369 27 command.c:364 register_command_handler(): registering ‘ocd_flash’...
Debug: 370 27 command.c:364 register_command_handler(): registering ‘ocd_flash’...
Debug: 371 27 command.c:364 register_command_handler(): registering ‘ocd_flash’...
Debug: 372 27 command.c:364 register_command_handler(): registering ‘ocd_flash’...
Debug: 373 27 command.c:143 script_debug(): command - ocd_command ocd_command type ocd_mflash init
Debug: 374 27 command.c:143 script_debug(): command - ocd_mflash ocd_mflash init
Debug: 376 28 mflash.c:1377 handle_mflash_init_command(): Initializing mflash devices...
Debug: 377 28 command.c:143 script_debug(): command - ocd_command ocd_command type ocd_nand init
Debug: 378 28 command.c:143 script_debug(): command - ocd_nand ocd_nand init
Debug: 380 28 tcl.c:497 handle_nand_init_command(): Initializing NAND devices...
Debug: 381 28 command.c:143 script_debug(): command - ocd_command ocd_command type ocd_pld init
Debug: 382 28 command.c:143 script_debug(): command - ocd_pld ocd_pld init
Debug: 384 29 pld.c:205 handle_pld_init_command(): Initializing PLDs...
Debug: 385 29 command.c:143 script_debug(): command - ocd_command ocd_command type ocd_reset init
Debug: 386 29 command.c:143 script_debug(): command - reset ocd_reset init
Debug: 388 29 target.c:1540 target_call_reset_callbacks(): target reset 3 (init)
Debug: 389 29 command.c:143 script_debug(): command - ocd_command ocd_command type ocd_target names
Debug: 390 29 command.c:143 script_debug(): command - ocd_target ocd_target names
Debug: 391 29 command.c:143 script_debug(): command - ocd_command ocd_command type ocd_STM32F405RGTx.cpu invoke-event reset-start
Debug: 392 29 command.c:143 script_debug(): command - ocd_STM32F405RGTx.cpu ocd_STM32F405RGTx.cpu invoke-event reset-start
Debug: 393 29 target.c:4429 target_handle_event(): target: (0) STM32F405RGTx.cpu (hla_target) event: 7 (reset-start) action:
if {using_jtag} {
adapter_khz 1125
} else {
adapter_khz 1800
}
Debug: 394 29 command.c:143 script_debug(): command - ocd_command ocd_command type ocd_transport select
Debug: 395 29 command.c:143 script_debug(): command - ocd_transport ocd_transport select
Debug: 396 29 command.c:143 script_debug(): command - ocd_command ocd_command type ocd_adapter_khz 1800
Debug: 397 29 command.c:143 script_debug(): command - adapter_khz ocd_adapter_khz 1800
Debug: 399 29 core.c:1631 jtag_config_khz(): handle jtag khz
Debug: 400 29 core.c:1598 adapter_khz_to_speed(): convert khz to interface specific speed value
Debug: 401 29 core.c:1601 adapter_khz_to_speed(): have interface set up
Info : 402 30 stlink_usb.c:2009 stlink_speed_v2(): Stlink adapter speed set to 1800 kHz
Debug: 403 30 core.c:1598 adapter_khz_to_speed(): convert khz to interface specific speed value
Debug: 404 30 core.c:1601 adapter_khz_to_speed(): have interface set up
User : 405 30 command.c:544 command_print(): adapter speed: 1800 kHz
Debug: 406 30 command.c:143 script_debug(): command - ocd_command ocd_command type ocd_transport select
Debug: 407 30 command.c:143 script_debug(): command - ocd_transport ocd_transport select
Debug: 408 30 command.c:143 script_debug(): command - ocd_command ocd_command type ocd_transport select
Debug: 409 30 command.c:143 script_debug(): command - ocd_transport ocd_transport select
Debug: 410 30 command.c:143 script_debug(): command - ocd_command ocd_command type ocd_STM32F405RGTx.cpu invoke-event examine-start
Debug: 411 30 command.c:143 script_debug(): command - ocd_STM32F405RGTx.cpu ocd_STM32F405RGTx.cpu invoke-event examine-start
Debug: 412 30 command.c:143 script_debug(): command - ocd_command ocd_command type ocd_STM32F405RGTx.cpu arp_examine allow-defer
Debug: 413 30 command.c:143 script_debug(): command - ocd_STM32F405RGTx.cpu ocd_STM32F405RGTx.cpu arp_examine allow-defer
Debug: 414 30 command.c:143 script_debug(): command - ocd_command ocd_command type ocd_STM32F405RGTx.cpu invoke-event examine-end
Debug: 415 30 command.c:143 script_debug(): command - ocd_STM32F405RGTx.cpu ocd_STM32F405RGTx.cpu invoke-event examine-end
Debug: 416 30 target.c:4429 target_handle_event(): target: (0) STM32F405RGTx.cpu (hla_target) event: 22 (examine-end) action:
global ENABLE_LOW_POWER
global STOP_WATCHDOG
if { expr ($ENABLE_LOW_POWER == 1) } {
# Enable debug during low power modes (uses more power)
# DBGMCU_CR |= DBG_STANDBY | DBG_STOP | DBG_SLEEP
mmw 0xE0042004 0x00000007 0
}
if { expr ($ENABLE_LOW_POWER == 0) } {
# Disable debug during low power modes
# DBGMCU_CR |= ~(DBG_STANDBY | DBG_STOP | DBG_SLEEP)
mmw 0xE0042004 0 0x00000007
}
if { expr ($STOP_WATCHDOG == 1) } {
# Stop watchdog counters during halt
# DBGMCU_APB1_FZ |= DBG_IWDG_STOP | DBG_WWDG_STOP
mmw 0xE0042008 0x00001800 0
}
if { expr ($STOP_WATCHDOG == 0) } {
# Don’t stop watchdog counters during halt
# DBGMCU_APB1_FZ |= ~(DBG_IWDG_STOP | DBG_WWDG_STOP)
mmw 0xE0042008 0 0x00001800
}
Debug: 417 30 hla_target.c:751 adapter_read_memory(): adapter_read_memory 0xe0042004 4 1
Debug: 418 31 command.c:143 script_debug(): command - ocd_command ocd_command type ocd_mww 0xE0042004 7
Debug: 419 31 command.c:143 script_debug(): command - mww ocd_mww 0xE0042004 7
Debug: 421 31 hla_target.c:766 adapter_write_memory(): adapter_write_memory 0xe0042004 4 1
Debug: 422 32 hla_target.c:751 adapter_read_memory(): adapter_read_memory 0xe0042008 4 1
Debug: 423 33 command.c:143 script_debug(): command - ocd_command ocd_command type ocd_mww 0xE0042008 6144
Debug: 424 33 command.c:143 script_debug(): command - mww ocd_mww 0xE0042008 6144
Debug: 426 33 hla_target.c:766 adapter_write_memory(): adapter_write_memory 0xe0042008 4 1
Debug: 427 33 command.c:143 script_debug(): command - ocd_command ocd_command type ocd_STM32F405RGTx.cpu invoke-event reset-assert-pre
Debug: 428 33 command.c:143 script_debug(): command - ocd_STM32F405RGTx.cpu ocd_STM32F405RGTx.cpu invoke-event reset-assert-pre
Debug: 429 34 command.c:143 script_debug(): command - ocd_command ocd_command type ocd_transport select
Debug: 430 34 command.c:143 script_debug(): command - ocd_transport ocd_transport select
Debug: 431 34 command.c:143 script_debug(): command - ocd_command ocd_command type ocd_STM32F405RGTx.cpu arp_reset assert 1
Debug: 432 34 command.c:143 script_debug(): command - ocd_STM32F405RGTx.cpu ocd_STM32F405RGTx.cpu arp_reset assert 1
Debug: 433 34 target.c:1920 target_free_all_working_areas_restore(): freeing all working areas
Debug: 434 34 hla_target.c:483 adapter_assert_reset(): adapter_assert_reset
Debug: 435 36 command.c:143 script_debug(): command - ocd_command ocd_command type ocd_STM32F405RGTx.cpu invoke-event reset-assert-post
Debug: 436 36 command.c:143 script_debug(): command - ocd_STM32F405RGTx.cpu ocd_STM32F405RGTx.cpu invoke-event reset-assert-post
Debug: 437 36 command.c:143 script_debug(): command - ocd_command ocd_command type ocd_STM32F405RGTx.cpu invoke-event reset-deassert-pre
Debug: 438 36 command.c:143 script_debug(): command - ocd_STM32F405RGTx.cpu ocd_STM32F405RGTx.cpu invoke-event reset-deassert-pre
Debug: 439 36 command.c:143 script_debug(): command - ocd_command ocd_command type ocd_transport select
Debug: 440 36 command.c:143 script_debug(): command - ocd_transport ocd_transport select
Debug: 441 36 command.c:143 script_debug(): command - ocd_command ocd_command type ocd_STM32F405RGTx.cpu arp_reset deassert 1
Debug: 442 36 command.c:143 script_debug(): command - ocd_STM32F405RGTx.cpu ocd_STM32F405RGTx.cpu arp_reset deassert 1
Debug: 443 36 target.c:1920 target_free_all_working_areas_restore(): freeing all working areas
Debug: 444 36 hla_target.c:546 adapter_deassert_reset(): adapter_deassert_reset
Debug: 445 36 hla_interface.c:127 hl_interface_execute_queue(): hl_interface_execute_queue: ignored
Debug: 446 36 core.c:729 jtag_add_reset(): SRST line released
Debug: 447 36 command.c:143 script_debug(): command - ocd_command ocd_command type ocd_STM32F405RGTx.cpu invoke-event reset-deassert-post
Debug: 448 36 command.c:143 script_debug(): command - ocd_STM32F405RGTx.cpu ocd_STM32F405RGTx.cpu invoke-event reset-deassert-post
Debug: 449 36 command.c:143 script_debug(): command - ocd_command ocd_command type ocd_transport select
Debug: 450 36 command.c:143 script_debug(): command - ocd_transport ocd_transport select
Debug: 451 36 command.c:143 script_debug(): command - ocd_command ocd_command type ocd_STM32F405RGTx.cpu was_examined
Debug: 452 36 command.c:143 script_debug(): command - ocd_STM32F405RGTx.cpu ocd_STM32F405RGTx.cpu was_examined
Debug: 453 36 command.c:143 script_debug(): command - ocd_command ocd_command type ocd_STM32F405RGTx.cpu arp_waitstate halted 1000
Debug: 454 37 command.c:143 script_debug(): command - ocd_STM32F405RGTx.cpu ocd_STM32F405RGTx.cpu arp_waitstate halted 1000
Debug: 455 37 target.c:2905 target_wait_state(): waiting for target halted...
Error: 457 1038 target.c:2913 target_wait_state(): timed out while waiting for target halted
Debug: 458 1038 command.c:143 script_debug(): command - ocd_command ocd_command type ocd_STM32F405RGTx.cpu curstate
Debug: 459 1038 command.c:143 script_debug(): command - ocd_STM32F405RGTx.cpu ocd_STM32F405RGTx.cpu curstate
User : 460 1038 command.c:544 command_print(): TARGET: STM32F405RGTx.cpu - Not halted
in procedure ‘program’
in procedure ‘reset’ called at file “embedded:startup.tcl”, line 490
in procedure ‘ocd_bouncer’
Debug: 461 1038 command.c:626 run_command(): Command failed with error code -4
Debug: 462 1038 command.c:143 script_debug(): command - ocd_command ocd_command type ocd_echo ** Unable to reset target **
Debug: 463 1038 command.c:143 script_debug(): command - echo ocd_echo ** Unable to reset target **
User : 465 1038 command.c:762 jim_echo(): ** Unable to reset target **
Debug: 466 1038 command.c:143 script_debug(): command - ocd_command ocd_command type ocd_shutdown error
Debug: 467 1039 command.c:143 script_debug(): command - shutdown ocd_shutdown error
User : 470 1039 server.c:652 handle_shutdown_command(): shutdown command invoked
Debug: 471 1039 command.c:626 run_command(): Command failed with error code -4
User : 472 1039 command.c:687 command_run_line():
Debug: 473 1039 hla_interface.c:117 hl_interface_quit(): hl_interface_quit
Debug: 474 1039 stlink_usb.c:934 stlink_exit_mode(): MODE: 0x02
Debug: 475 1039 stlink_usb.c:955 stlink_exit_mode(): E-MODE: 0x04
;){kind=link}