Unable Halt CPU During Debug
Have installed System Workbench for STM32 (install_sw4stm32_win_64bits-v1.8.zip) on a Windows 10 (64-bit) platform and also updated it using Help|Check for Updates. I am using an ST-LINK/V2 debug probe which I recently updated to F/W V2.J28.S6 and am able to successfully see the probe using ST-LINK Utility. In Control Panel|System|Device Manager I can see the entry USB Serial Bus devices|STM32 STLink and its driver version is V1.1 (21/01/2013).
My project has been generated using STM32CubeMX V4.18 (STM32Cube V1.0) and imported into System Workbench which successfully builds. As the project was imported I was presented with the “No board found : Define new board or ..” dialogue box and so created a new board type (since the hardware was a custom design). Here I selected Select series: STM32F4, Select mpu: STM32F411RETx, Debug device: ST-LinkV2 and Debug interface: SWD. On closing this dialogue I see that the Main, Debugger, Startup, Source and Common tabs appear to contain sensible settings.
No code other than that generated by STM32CubeMX has been added yet.
On inspection of the script at Debugger|Script:|Configuration Script I can see two lines (starting with “source”) as follows.
source find interface/stlink-v2.cfg
source find target/stm32f4x_stlink.cfg
And both the *.cfg files exist (twice) within the ...\resources\scripts\target directory.
The problem I have is when I attempt to debug and System Workbench connects to the ST-Link/V2 probe (presumably via openOCD) I get the Problem Occurred dialogue box as follows.
Error in final launch sequence
Failed to execute MI command:
load C:\david\proj\stm32f411_sample\Debug\stm32f411_sample.elf
Error message from debugger back end:
Error erasing flash with vFlashErase packet
Error erasing flash with vFlashErase packet
And the console date is as follows.
Open On-Chip Debugger 0.10.0-dev-00273-g394abef (2016-11-24-15:15)
Licensed under GNU GPL v2
For bug reports, read
http://openocd.org/doc/doxygen/bugs.html
Info : The selected transport took over low-level target control. The results might differ compared to plain JTAG/SWD
adapter speed: 2000 kHz
adapter_nsrst_delay: 100
srst_only separate srst_nogate srst_open_drain connect_assert_srst
srst_only separate srst_nogate srst_open_drain connect_assert_srst
Info : Unable to match requested speed 2000 kHz, using 1800 kHz
Info : Unable to match requested speed 2000 kHz, using 1800 kHz
Info : clock speed 1800 kHz
Info : STLINK v2 JTAG v28 API v2 SWIM v6 VID 0x0483 PID 0x3748
Info : using stlink api v2
Info : Target voltage: 3.011082
Info : STM32F411RETx.cpu: hardware has 6 breakpoints, 4 watchpoints
Info : accepting ‘gdb’ connection on tcp/3333
Info : Unable to match requested speed 2000 kHz, using 1800 kHz
Info : Unable to match requested speed 2000 kHz, using 1800 kHz
adapter speed: 1800 kHz
Error: timed out while waiting for target halted
TARGET: STM32F411RETx.cpu - Not halted
in procedure ‘reset’
in procedure ‘ocd_bouncer’
Info : device id = 0x10006431
Info : flash size = 256kbytes
Info : Unable to match requested speed 2000 kHz, using 1800 kHz
Info : Unable to match requested speed 2000 kHz, using 1800 kHz
adapter speed: 1800 kHz
Error: timed out while waiting for target halted
TARGET: STM32F411RETx.cpu - Not halted
in procedure ‘reset’
in procedure ‘ocd_bouncer’
Info : Unable to match requested speed 2000 kHz, using 1800 kHz
Info : Unable to match requested speed 2000 kHz, using 1800 kHz
adapter speed: 1800 kHz
Error: timed out while waiting for target halted
TARGET: STM32F411RETx.cpu - Not halted
in procedure ‘reset’
in procedure ‘ocd_bouncer’
Error: Target not halted
Error: failed erasing sectors 0 to 0
Error: flash_erase returned -304
Which appears to me to suggest that there was a connection to the target (beacuse it read its voltage) but is not able to force it to halt and there unable to download to its flash.
I am able to successfully access the target for erase and programming purposes using STM32 ST-LINT Utility (V4.0.0.0).
Any help as to why I am not able to debug this target would be appreciated.