SW4STM32 and SW4Linux fully supports the STM32MP1 asymmetric multicore Cortex/A7+M4 MPUs

   With System Workbench for Linux, Embedded Linux on the STM32MP1 family of MPUs from ST was never as simple to build and maintain, even for newcomers in the Linux world.
And, if you install System Workbench for Linux in System Workbench for STM32 you can seamlessly develop and debug asymmetric applications running partly on Linux, partly on the Cortex-M4.
You can get more information from the ac6-tools website and download two short videos (registration required) highlighting:

System Workbench for STM32

STM32L4 linker script for 128 KB RAM

Hi ST support,

I’m using STM32L476RG-Nucleo with the last eclipse framework v1.3.0.

I was surprised by the fact that the generated linker script only offers 96 KB RAM.
It appears that this mcu RAM is split in SRAM1 and SRAM2 which are NOT contiguous.

I don’t care where my RAM data is allocated but I need 128 K.

Forcing 128K in the generated linker script make the execution fail as the RAM region are NOT contiguous.

Is it a possibility to define the two sections and link RAM data in these regions without explicitely setting the mapping.
To do that, the linker must look for the best data arrangement to respect the RAM region mapping and I figure this is NOT implemented so it’s mandatory to set the mapping.

Any corrections to my assumptions / suggestions ?

Thanks and regards,

I tried to allocate my OS heap in SRAM2 that way:

Source C code:
static uint8_t attribute ((section (“RAM_2”))) ucHeap configTOTAL_HEAP_SIZE ;

Linker script: definiing the section:
RAM_2 (xrw) : ORIGIN = 0x10000000, LENGTH = 32K

But doing this is NOT working: gcc allocate a section RAM_2 in classic RAM section and ucHeap won’t reside in RAM_2 section defined in linker script.

Can you provide the right way to do this ?

thanks and regards,

I solved my own issue using a previous post on the forum:

here is a solution:
linker script:

region definitions:

RAM (xrw) : ORIGIN = 0x20000000, LENGTH = 96K
RAM_2 (xrw) : ORIGIN = 0x10000000, LENGTH = 32K

in section definitions:

.ram2_bss :
. = ALIGN(4);

} >RAM_2

C source code:
static uint8_t attribute ((section (“.ram2_bss”), used)) ucHeap configTOTAL_HEAP_SIZE ;


Hi ST support,

I’m using STM32L476RG-Nucleo, AC6 IDE generated linker script only offers 96 KB RAM.

My need application more RAM, can I use 32 KB which is SRAM2 as below.

32 Kbyte located at address 0x1000 0000 with hardware parity check (SRAM2)

Best regards,