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Flash write failed when connecting to STM32H753IIK

Hello OpenSTM32 Community,

I faced a problem that I could not connect to STM32H753IIK via ST-LINK/v2 (or ST-LINK/v2-1 on Nucleo-H743ZI). OpenSTM32 version is v2.7.

Even the same configuration successfully connects to STM32H743ZIT6 on Nucleo-H743ZI, but failed for STM32H753IIK. The target is wired by Nucleo onboard ST-LINK/v2-1 as described on STM document UM1974 (section 6.3.4 Using ST-LINK/V2-1 to program and debug an external STM32 application). NRST pin is also connected.

I saw the following error on the console. I confirmed that OpenSTM32 v2.7 for Mac OS and Windows both failed similarly.

Open On-Chip Debugger 0.10.0-dev-00015-gaaf1808 (2018-11-13-12:57)
Licensed under GNU GPL v2
For bug reports, read
http://openocd.org/doc/doxygen/bugs.html
srst_only separate srst_nogate srst_open_drain connect_assert_srst
Info : The selected transport took over low-level target control. The results might differ compared to plain JTAG/SWD
adapter_nsrst_delay: 100
adapter speed: 1800 kHz
Info : clock speed 1800 kHz
Info : STLINK v2.1 JTAG v29 API v2 M18 VID 0x0483 PID 0x374B
Info : using stlink api v2
Info : Target voltage: 3.236220
Info : Stlink adapter speed set to 1800 kHz
Info : STM32H753IIKx.cpu: hardware has 8 breakpoints, 4 watchpoints
Info : accepting ‘gdb’ connection on tcp/3333
target halted due to debug-request, current mode: Thread
xPSR: 0x01000000 pc: 0xfffffffe msp: 0xfffffffc
Info : Stlink adapter speed set to 4000 kHz
adapter speed: 4000 kHz
Info : Device: STM32H7xx 2M
Info : flash size probed value 2048
Info : STM32H flash has dual banks. Bank (0) size is 1024kb, base address is 0x8000000
Info : Device: STM32H7xx 2M
Info : flash size probed value 2048
Info : STM32H flash has dual banks. Bank (1) size is 1024kb, base address is 0x8100000
target halted due to debug-request, current mode: Thread
xPSR: 0x01000000 pc: 0xfffffffe msp: 0xfffffffc
Info : Stlink adapter speed set to 4000 kHz
adapter speed: 4000 kHz
Info : Padding image section 0 with 8 bytes
Error: flash write algorithm aborted by target
Info : error executing stm32h7x flash write algorithm
Error: flash write failed, FLASH_SR = 00050000
Error: error writing to flash at address 0x08000000 at offset 0x00000000
target halted due to debug-request, current mode: Thread
xPSR: 0x01000000 pc: 0xfffffffe msp: 0xfffffffc
Info : Stlink adapter speed set to 4000 kHz
adapter speed: 4000 kHz

By the way, by the same wiring, ST-LINK Utility can flash without any problem.

FYI, when connecting to STM32H743ZIT6 on Nucleo-H743ZI, I saw

Info : STLINK v2.1 JTAG v29 API v2 M18 VID 0x0483 PID 0x374B
Info : using stlink api v2
Info : Target voltage: 3.240945
Info : Stlink adapter speed set to 1800 kHz
Info : STM32H753IIKx.cpu: hardware has 8 breakpoints, 4 watchpoints
Info : accepting ‘gdb’ connection on tcp/3333
target halted due to debug-request, current mode: Thread
xPSR: 0x01000000 pc: 0x08003274 msp: 0x20020000
Info : Stlink adapter speed set to 4000 kHz
adapter speed: 4000 kHz
Info : Device: STM32H7xx 2M
Info : flash size probed value 2048
Info : STM32H flash has dual banks. Bank (0) size is 1024kb, base address is 0x8000000
Info : Device: STM32H7xx 2M
Info : flash size probed value 2048
Info : STM32H flash has dual banks. Bank (1) size is 1024kb, base address is 0x8100000
target halted due to debug-request, current mode: Thread
xPSR: 0x01000000 pc: 0x08003274 msp: 0x20020000
Info : Stlink adapter speed set to 4000 kHz
adapter speed: 4000 kHz
Info : Padding image section 0 with 8 bytes
target halted due to breakpoint, current mode: Thread
xPSR: 0x61000000 pc: 0x20000052 msp: 0x20020000
target halted due to debug-request, current mode: Thread
xPSR: 0x01000000 pc: 0x08003274 msp: 0x20020000
Info : Stlink adapter speed set to 4000 kHz
adapter speed: 4000 kHz

Any suggestion would be appreciated.

Regards,
Atsushi

Noticed one difference.

The device successfully flashed is “Device ID Y” (found on Nucleo).
The device not-successfully flashed is, “Device ID X” (new revision).

Refer “STM32H750xB and STM32H753xI Errata sheet (ES0396 Rev 4)”.
I suspect that we may need different flash writing procedure between the two device revisions...

Regards,
Atsushi

Hello,

Indeed, H7xx rev X needs an update for flash writing, a new version will be available soon to correct this.

Rgds,
Laurent

Hi Laurent,

Thank you for your reply! Before reading the reply, I think I found a possible solution.

In OpenOCD source code src/flash/nor/stm32h7x.c, I added the following line.

target_write_u32(target, stm32x_get_flash_reg(bank, FLASH_CR), FLASH_PG);

just prior calling “target_run_flash_async_algorithm()”.

By the change, the problem looks resolved.

I’m not sure if this is the case and why revision Y doesn’t complain about PG bit.

Once again, thank you for your attention.

Regards,
Atsushi

I found assembly code stm32h7x.S is actually setting PG bit as following.

define STM32_CR_PROG 0x00000032 /* PSIZE64 | PG */
// ...
mov r6, #STM32_CR_PROG
str r6, r4, #STM32_FLASH_CR_OFFSET

I’m confused.

I’m waiting for an analysis by specialists.

Regards,
Atsushi

Hello,

The issue was not with the PG bit but more with the QW bit when polling the programming status.
You can try the latest version SW4STM32 V2.8.0.
It includes the correction and should work now on all H7 revisions.

Rgds,
Laurent

Hi Laurent,

Thank you for the update. I will try the latest version ASAP.

Regards,
Atsushi

Hi Laurent,

Confirmed that SW4STM32 v2.8 (Windows version) could flash rev X of STM32H753. Thank you for your support!

Regards,
Atsushi