System Workbench for STM32

Hello MSchultz,

thanks for your reply.
Of course I configure the DMA registers only if DMA is disabled and the ADC is after initialisation and calibration always in idle mode to avoid delays.
The Initialisation sequenz I use ist mostly the same you have described. But may be the ADCs of F0 and F3 are a little different to F1 because some register bits or registers are not available in F103 (ADC_CFGR1_DMACFG, ADC_CR_ADSTART, ADC_CR_ADDIS ...). I dont use Standart Peripheral Library but HAL-Driver, so some abbreviations may be different. Like you I dont use library functions but work on register level.

The mayor difference I see, is that you use the interrupt and clear interrupt bits. I only read results of conversion every ms without interrupt and I don´t clear interrupt bits. In my opinion there is a difference between interrupt and DMA request. Interrupt occures only at the end of conversion sequenz, DMA request but after every single conversion. In earlyer applications (with µVision from Keil) I only disabled DMA (ADC has finished) and then reenabled DMA and enabled ADC. All works fine without notice of interrupt bits. Now with SW4STM32 and HAL libraries (I dont know if this is the problem) it seems that a DMA request is pending after ADC has finished and data are read as soon as DMA is enabled though the ADC is not enabled.

Now when I read the ADC_DR register and clear and set the ADC_CR2_DMA bit it works like expected (last days trial).

I´m confused about that. This was not was I expected. Are there relations between ADC interrupt bit and DMA request bit.
STs manuals are not sufficient in view of that.

Leo