flashing STM32L433CCT6 failed
Hi
I’m trying to flash an STM32L433CCT6 with AC6 via openocd and one of these cheap ST-Link V2 Adapters.
I have changed scripts/target/stm32l4x.cfg because otherwise the MCU gets not halted.
#reset_config srst_only srst_nogate connect_assert_srst #modified line: reset_config srst_nogate connect_assert_srst
My local OpenOCD script is as folliwing:
source [find interface/stlink-v2.cfg] set WORKAREASIZE 0xC000 transport select "hla_swd" set CHIPNAME STM32L433CCTx source [find target/stm32l4x.cfg] reset_config srst_nogate
Console output of OpenOCD:
adapter speed: 500 kHz adapter_nsrst_delay: 100 none separate none separate Info : Unable to match requested speed 500 kHz, using 480 kHz Info : Unable to match requested speed 500 kHz, using 480 kHz Info : clock speed 480 kHz Info : STLINK v2 JTAG v17 API v2 SWIM v4 VID 0x0483 PID 0x3748 Info : using stlink api v2 Info : Target voltage: 3.229669 Info : STM32L433CCTx.cpu: hardware has 6 breakpoints, 4 watchpoints STM32L433CCTx.cpu: target state: halted target halted due to debug-request, current mode: Thread xPSR: 0x01000000 pc: 0x1fff3f36 msp: 0x20002c20 adapter speed: 4000 kHz ** Programming Started ** auto erase enabled Info : Device id = 0x10016435 Info : STM32L4xx flash size is 256kb, base address is 0x8000000 Error: jtag status contains invalid mode value - communication failure Error: error waiting for target flash write algorithm Error: error writing to flash at address 0x08000000 at offset 0x00000000 Info : Previous state query failed, trying to reconnect ** Programming Failed ** shutdown command invoked
I did a full debug session of OpenOCD on the console invoking
LD_LIBRARY_PATH=/home/db/.p2/pool/plugins/fr.ac6.mcu.externaltools.openocd.linux64_1.12.0.201611241417/tools/openocd/lib/ /home/db/.p2/pool/plugins/fr.ac6.mcu.externaltools.openocd.linux64_1.12.0.201611241417/tools/openocd/bin/openocd -f /array_data01/STM32L433CCTx-mini-sys-01/L433CCTx-mini-sys/L433CCT6-mini-sys.cfg -d 3
OpenOCD messages:
Debug: 141 3 command.c:145 script_debug(): command - ocd_command ocd_command type ocd_STM32L433CCTx.cpu configure -work-area-phys 0x20000000 -work-area-size 0xC000 -work-area-backup 0
Debug: 142 3 command.c:145 script_debug(): command - ocd_STM32L433CCTx.cpu ocd_STM32L433CCTx.cpu configure -work-area-phys 0x20000000 -work-area-size 0xC000 -work-area-backup 0
Debug: 143 3 target.c:1883 target_free_all_working_areas_restore(): freeing all working areas
Debug: 144 3 target.c:1883 target_free_all_working_areas_restore(): freeing all working areas
Debug: 145 3 target.c:1883 target_free_all_working_areas_restore(): freeing all working areas
Debug: 146 3 command.c:145 script_debug(): command - ocd_command ocd_command type ocd_flash bank STM32L433CCTx.flash stm32l4x 0 0 0 0 STM32L433CCTx.cpu
Debug: 147 3 command.c:145 script_debug(): command - ocd_flash ocd_flash bank STM32L433CCTx.flash stm32l4x 0 0 0 0 STM32L433CCTx.cpu
Debug: 149 3 command.c:366 register_command_handler(): registering 'ocd_stm32l4x'...
Debug: 150 3 command.c:366 register_command_handler(): registering 'ocd_stm32l4x'...
Debug: 151 3 command.c:366 register_command_handler(): registering 'ocd_stm32l4x'...
Debug: 152 3 command.c:366 register_command_handler(): registering 'ocd_stm32l4x'...
Debug: 153 3 command.c:366 register_command_handler(): registering 'ocd_stm32l4x'...
Debug: 154 3 command.c:366 register_command_handler(): registering 'ocd_stm32l4x'...
Debug: 155 3 command.c:366 register_command_handler(): registering 'ocd_stm32l4x'...
Debug: 156 3 tcl.c:1031 handle_flash_bank_command(): 'stm32l4x' driver usage field missing
Debug: 157 3 command.c:145 script_debug(): command - ocd_command ocd_command type ocd_adapter_khz 500
Debug: 158 3 command.c:145 script_debug(): command - adapter_khz ocd_adapter_khz 500
Debug: 160 3 core.c:1633 jtag_config_khz(): handle jtag khz
Debug: 161 3 core.c:1600 adapter_khz_to_speed(): convert khz to interface specific speed value
Debug: 162 3 core.c:1600 adapter_khz_to_speed(): convert khz to interface specific speed value
User : 163 3 command.c:546 command_print(): adapter speed: 500 kHz
Debug: 164 3 command.c:145 script_debug(): command - ocd_command ocd_command type ocd_adapter_nsrst_delay 100
Debug: 165 3 command.c:145 script_debug(): command - adapter_nsrst_delay ocd_adapter_nsrst_delay 100
User : 167 3 command.c:546 command_print(): adapter_nsrst_delay: 100
Debug: 168 3 command.c:145 script_debug(): command - ocd_command ocd_command type ocd_transport select
Debug: 169 3 command.c:145 script_debug(): command - ocd_transport ocd_transport select
Debug: 170 3 command.c:145 script_debug(): command - ocd_command ocd_command type ocd_reset_config srst_nogate connect_assert_srst
Debug: 171 3 command.c:145 script_debug(): command - reset_config ocd_reset_config srst_nogate connect_assert_srst
User : 173 3 command.c:546 command_print(): none separate
Debug: 174 3 command.c:145 script_debug(): command - ocd_command ocd_command type ocd_transport select
Debug: 175 3 command.c:145 script_debug(): command - ocd_transport ocd_transport select
Debug: 176 3 command.c:145 script_debug(): command - ocd_command ocd_command type ocd_STM32L433CCTx.cpu configure -event reset-init
# CPU comes out of reset with MSI_ON | MSI_RDY | MSI Range 6 (4 MHz).
# Configure system to use MSI 24 MHz clock, compliant with VOS default (2).
# 3 WS compliant with VOS=2 and 24 MHz.
mww 0x40022000 0x00000102 ;# FLASH_ACR = PRFTBE | 3(Latency)
mww 0x4002100C 0x00000099 ;# RCC_CR = MSI_ON | MSIRGSEL| MSI Range 10
# Boost JTAG frequency
adapter_khz 4000
Debug: 177 3 command.c:145 script_debug(): command - ocd_STM32L433CCTx.cpu ocd_STM32L433CCTx.cpu configure -event reset-init
# CPU comes out of reset with MSI_ON | MSI_RDY | MSI Range 6 (4 MHz).
# Configure system to use MSI 24 MHz clock, compliant with VOS default (2).
# 3 WS compliant with VOS=2 and 24 MHz.
mww 0x40022000 0x00000102 ;# FLASH_ACR = PRFTBE | 3(Latency)
mww 0x4002100C 0x00000099 ;# RCC_CR = MSI_ON | MSIRGSEL| MSI Range 10
# Boost JTAG frequency
adapter_khz 4000
Debug: 178 3 command.c:145 script_debug(): command - ocd_command ocd_command type ocd_STM32L433CCTx.cpu configure -event examine-end
# DBGMCU_CR |= DBG_STANDBY | DBG_STOP | DBG_SLEEP
mmw 0xE0042004 0x00000007 0
# Stop watchdog counters during halt
# DBGMCU_APB1_FZ |= DBG_IWDG_STOP | DBG_WWDG_STOP
mmw 0xE0042008 0x00001800 0
Debug: 179 3 command.c:145 script_debug(): command - ocd_STM32L433CCTx.cpu ocd_STM32L433CCTx.cpu configure -event examine-end
# DBGMCU_CR |= DBG_STANDBY | DBG_STOP | DBG_SLEEP
mmw 0xE0042004 0x00000007 0
# Stop watchdog counters during halt
# DBGMCU_APB1_FZ |= DBG_IWDG_STOP | DBG_WWDG_STOP
mmw 0xE0042008 0x00001800 0
Debug: 180 3 command.c:145 script_debug(): command - ocd_command ocd_command type ocd_STM32L433CCTx.cpu configure -event trace-config
# Set TRACE_IOEN; TRACE_MODE is set to async; when using sync
# change this value accordingly to configure trace pins
# assignment
mmw 0xE0042004 0x00000020 0
Debug: 181 3 command.c:145 script_debug(): command - ocd_STM32L433CCTx.cpu ocd_STM32L433CCTx.cpu configure -event trace-config
# Set TRACE_IOEN; TRACE_MODE is set to async; when using sync
# change this value accordingly to configure trace pins
# assignment
mmw 0xE0042004 0x00000020 0
Debug: 182 3 command.c:145 script_debug(): command - ocd_command ocd_command type ocd_STM32L433CCTx.cpu configure -event gdb-attach
# Needed to be able to use the connect_assert_srst in reset_config
# otherwise, wrong value when reading device flash size register
reset init
Debug: 183 3 command.c:145 script_debug(): command - ocd_STM32L433CCTx.cpu ocd_STM32L433CCTx.cpu configure -event gdb-attach
# Needed to be able to use the connect_assert_srst in reset_config
# otherwise, wrong value when reading device flash size register
reset init
Debug: 184 3 command.c:145 script_debug(): command - ocd_command ocd_command type ocd_reset_config srst_nogate
Debug: 185 3 command.c:145 script_debug(): command - reset_config ocd_reset_config srst_nogate
User : 187 3 command.c:546 command_print(): none separate
Debug: 188 3 command.c:145 script_debug(): command - ocd_command ocd_command type ocd_init
Debug: 189 3 command.c:145 script_debug(): command - init ocd_init
Debug: 191 3 command.c:145 script_debug(): command - ocd_command ocd_command type ocd_target init
Debug: 192 4 command.c:145 script_debug(): command - ocd_target ocd_target init
Debug: 194 4 command.c:145 script_debug(): command - ocd_command ocd_command type ocd_target names
Debug: 195 4 command.c:145 script_debug(): command - ocd_target ocd_target names
Debug: 196 4 command.c:145 script_debug(): command - ocd_command ocd_command type ocd_STM32L433CCTx.cpu cget -event gdb-flash-erase-start
Debug: 197 4 command.c:145 script_debug(): command - ocd_STM32L433CCTx.cpu ocd_STM32L433CCTx.cpu cget -event gdb-flash-erase-start
Debug: 198 4 command.c:145 script_debug(): command - ocd_command ocd_command type ocd_STM32L433CCTx.cpu configure -event gdb-flash-erase-start reset init
Debug: 199 4 command.c:145 script_debug(): command - ocd_STM32L433CCTx.cpu ocd_STM32L433CCTx.cpu configure -event gdb-flash-erase-start reset init
Debug: 200 4 command.c:145 script_debug(): command - ocd_command ocd_command type ocd_STM32L433CCTx.cpu cget -event gdb-flash-write-end
Debug: 201 4 command.c:145 script_debug(): command - ocd_STM32L433CCTx.cpu ocd_STM32L433CCTx.cpu cget -event gdb-flash-write-end
Debug: 202 4 command.c:145 script_debug(): command - ocd_command ocd_command type ocd_STM32L433CCTx.cpu configure -event gdb-flash-write-end reset halt
Debug: 203 4 command.c:145 script_debug(): command - ocd_STM32L433CCTx.cpu ocd_STM32L433CCTx.cpu configure -event gdb-flash-write-end reset halt
Debug: 204 4 target.c:1308 handle_target_init_command(): Initializing targets...
Debug: 205 4 hla_target.c:343 adapter_init_target(): adapter_init_target
Debug: 206 4 command.c:366 register_command_handler(): registering 'ocd_target_request'...
Debug: 207 4 command.c:366 register_command_handler(): registering 'ocd_trace'...
Debug: 208 4 command.c:366 register_command_handler(): registering 'ocd_trace'...
Debug: 209 4 command.c:366 register_command_handler(): registering 'ocd_fast_load_image'...
Debug: 210 4 command.c:366 register_command_handler(): registering 'ocd_fast_load'...
Debug: 211 4 command.c:366 register_command_handler(): registering 'ocd_profile'...
Debug: 212 4 command.c:366 register_command_handler(): registering 'ocd_virt2phys'...
Debug: 213 4 command.c:366 register_command_handler(): registering 'ocd_reg'...
Debug: 214 4 command.c:366 register_command_handler(): registering 'ocd_poll'...
Debug: 215 4 command.c:366 register_command_handler(): registering 'ocd_wait_halt'...
Debug: 216 4 command.c:366 register_command_handler(): registering 'ocd_halt'...
Debug: 217 4 command.c:366 register_command_handler(): registering 'ocd_resume'...
Debug: 218 4 command.c:366 register_command_handler(): registering 'ocd_reset'...
Debug: 219 4 command.c:366 register_command_handler(): registering 'ocd_soft_reset_halt'...
Debug: 220 4 command.c:366 register_command_handler(): registering 'ocd_step'...
Debug: 221 4 command.c:366 register_command_handler(): registering 'ocd_mdw'...
Debug: 222 4 command.c:366 register_command_handler(): registering 'ocd_mdh'...
Debug: 223 4 command.c:366 register_command_handler(): registering 'ocd_mdb'...
Debug: 224 4 command.c:366 register_command_handler(): registering 'ocd_mww'...
Debug: 225 4 command.c:366 register_command_handler(): registering 'ocd_mwh'...
Debug: 226 4 command.c:366 register_command_handler(): registering 'ocd_mwb'...
Debug: 227 4 command.c:366 register_command_handler(): registering 'ocd_bp'...
Debug: 228 4 command.c:366 register_command_handler(): registering 'ocd_rbp'...
Debug: 229 4 command.c:366 register_command_handler(): registering 'ocd_wp'...
Debug: 230 4 command.c:366 register_command_handler(): registering 'ocd_rwp'...
Debug: 231 4 command.c:366 register_command_handler(): registering 'ocd_load_image'...
Debug: 232 4 command.c:366 register_command_handler(): registering 'ocd_dump_image'...
Debug: 233 4 command.c:366 register_command_handler(): registering 'ocd_verify_image'...
Debug: 234 4 command.c:366 register_command_handler(): registering 'ocd_test_image'...
Debug: 235 4 command.c:366 register_command_handler(): registering 'ocd_reset_nag'...
Debug: 236 4 command.c:366 register_command_handler(): registering 'ocd_ps'...
Debug: 237 4 command.c:366 register_command_handler(): registering 'ocd_test_mem_access'...
Debug: 238 4 hla_interface.c:111 hl_interface_init(): hl_interface_init
Debug: 239 4 hla_layout.c:85 hl_layout_init(): hl_layout_init
Debug: 240 4 core.c:1600 adapter_khz_to_speed(): convert khz to interface specific speed value
Debug: 241 4 core.c:1603 adapter_khz_to_speed(): have interface set up
Info : 242 4 stlink_usb.c:1664 stlink_speed(): Unable to match requested speed 500 kHz, using 480 kHz
Debug: 243 4 core.c:1600 adapter_khz_to_speed(): convert khz to interface specific speed value
Debug: 244 4 core.c:1603 adapter_khz_to_speed(): have interface set up
Info : 245 4 stlink_usb.c:1664 stlink_speed(): Unable to match requested speed 500 kHz, using 480 kHz
Info : 246 4 core.c:1388 adapter_init(): clock speed 480 kHz
Debug: 247 4 openocd.c:137 handle_init_command(): Debug Adapter init complete
Debug: 248 4 command.c:145 script_debug(): command - ocd_command ocd_command type ocd_transport init
Debug: 249 4 command.c:145 script_debug(): command - ocd_transport ocd_transport init
Debug: 251 4 transport.c:240 handle_transport_init(): handle_transport_init
Debug: 252 4 hla_transport.c:154 hl_transport_init(): hl_transport_init
Debug: 253 4 hla_transport.c:171 hl_transport_init(): current transport hla_swd
Debug: 254 4 hla_interface.c:44 hl_interface_open(): hl_interface_open
Debug: 255 4 hla_layout.c:42 hl_layout_open(): hl_layout_open
Debug: 256 4 stlink_usb.c:1698 stlink_usb_open(): stlink_usb_open
Debug: 257 4 stlink_usb.c:1716 stlink_usb_open(): transport: 1 vid: 0x0483 pid: 0x3748 serial:
Info : 258 8 stlink_usb.c:619 stlink_usb_version(): STLINK v2 JTAG v17 API v2 SWIM v4 VID 0x0483 PID 0x3748
Info : 259 8 stlink_usb.c:1834 stlink_usb_open(): using stlink api v2
Debug: 260 10 stlink_usb.c:818 stlink_usb_init_mode(): MODE: 0x02
Info : 261 15 stlink_usb.c:651 stlink_usb_check_voltage(): Target voltage: 3.228079
Debug: 262 15 stlink_usb.c:873 stlink_usb_init_mode(): MODE: 0x01
Debug: 263 20 stlink_usb.c:899 stlink_usb_init_mode(): MODE: 0x02
Debug: 264 24 stlink_usb.c:1872 stlink_usb_open(): Using TAR autoincrement: 4096
Error: 265 24 core.c:677 jtag_add_reset(): BUG: can't assert SRST
Debug: 266 26 hla_interface.c:69 hl_interface_init_target(): hl_interface_init_target
Debug: 267 28 stlink_usb.c:924 stlink_usb_idcode(): IDCODE: 0x2BA01477
Debug: 268 28 openocd.c:150 handle_init_command(): Examining targets...
Debug: 269 28 target.c:1501 target_call_event_callbacks(): target event 21 (examine-start)
Debug: 270 28 hla_target.c:752 adapter_read_memory(): adapter_read_memory 0xe000ed00 4 1
Debug: 271 32 target.c:2226 target_read_u32(): address: 0xe000ed00, value: 0x410fc241
Debug: 272 32 cortex_m.c:1933 cortex_m_examine(): Cortex-M4 r0p1 processor detected
Debug: 273 32 cortex_m.c:1941 cortex_m_examine(): cpuid: 0x410fc241
Debug: 274 32 hla_target.c:752 adapter_read_memory(): adapter_read_memory 0xe000ef40 4 1
Debug: 275 36 target.c:2226 target_read_u32(): address: 0xe000ef40, value: 0x10110021
Debug: 276 36 hla_target.c:752 adapter_read_memory(): adapter_read_memory 0xe000ef44 4 1
Debug: 277 40 target.c:2226 target_read_u32(): address: 0xe000ef44, value: 0x11000011
Debug: 278 40 cortex_m.c:1949 cortex_m_examine(): Cortex-M4 floating point feature FPv4_SP found
Debug: 279 40 target.c:2314 target_write_u32(): address: 0xe000edfc, value: 0x01000000
Debug: 280 40 hla_target.c:766 adapter_write_memory(): adapter_write_memory 0xe000edfc 4 1
Debug: 281 44 hla_target.c:752 adapter_read_memory(): adapter_read_memory 0xe0002000 4 1
Debug: 282 48 target.c:2226 target_read_u32(): address: 0xe0002000, value: 0x00000260
Debug: 283 48 target.c:2314 target_write_u32(): address: 0xe0002008, value: 0x00000000
Debug: 284 48 hla_target.c:766 adapter_write_memory(): adapter_write_memory 0xe0002008 4 1
Debug: 285 52 target.c:2314 target_write_u32(): address: 0xe000200c, value: 0x00000000
Debug: 286 52 hla_target.c:766 adapter_write_memory(): adapter_write_memory 0xe000200c 4 1
Debug: 287 56 target.c:2314 target_write_u32(): address: 0xe0002010, value: 0x00000000
Debug: 288 56 hla_target.c:766 adapter_write_memory(): adapter_write_memory 0xe0002010 4 1
Debug: 289 60 target.c:2314 target_write_u32(): address: 0xe0002014, value: 0x00000000
Debug: 290 60 hla_target.c:766 adapter_write_memory(): adapter_write_memory 0xe0002014 4 1
Debug: 291 64 target.c:2314 target_write_u32(): address: 0xe0002018, value: 0x00000000
Debug: 292 64 hla_target.c:766 adapter_write_memory(): adapter_write_memory 0xe0002018 4 1
Debug: 293 68 target.c:2314 target_write_u32(): address: 0xe000201c, value: 0x00000000
Debug: 294 68 hla_target.c:766 adapter_write_memory(): adapter_write_memory 0xe000201c 4 1
Debug: 295 72 target.c:2314 target_write_u32(): address: 0xe0002020, value: 0x00000000
Debug: 296 72 hla_target.c:766 adapter_write_memory(): adapter_write_memory 0xe0002020 4 1
Debug: 297 76 target.c:2314 target_write_u32(): address: 0xe0002024, value: 0x00000000
Debug: 298 76 hla_target.c:766 adapter_write_memory(): adapter_write_memory 0xe0002024 4 1
Debug: 299 80 cortex_m.c:2032 cortex_m_examine(): FPB fpcr 0x260, numcode 6, numlit 2
Debug: 300 80 hla_target.c:752 adapter_read_memory(): adapter_read_memory 0xe0001000 4 1
Debug: 301 84 target.c:2226 target_read_u32(): address: 0xe0001000, value: 0x40000000
Debug: 302 84 target.c:2314 target_write_u32(): address: 0xe0001028, value: 0x00000000
Debug: 303 84 hla_target.c:766 adapter_write_memory(): adapter_write_memory 0xe0001028 4 1
Debug: 304 88 target.c:2314 target_write_u32(): address: 0xe0001038, value: 0x00000000
Debug: 305 88 hla_target.c:766 adapter_write_memory(): adapter_write_memory 0xe0001038 4 1
Debug: 306 92 target.c:2314 target_write_u32(): address: 0xe0001048, value: 0x00000000
Debug: 307 92 hla_target.c:766 adapter_write_memory(): adapter_write_memory 0xe0001048 4 1
Debug: 308 96 target.c:2314 target_write_u32(): address: 0xe0001058, value: 0x00000000
Debug: 309 96 hla_target.c:766 adapter_write_memory(): adapter_write_memory 0xe0001058 4 1
Debug: 310 100 cortex_m.c:1847 cortex_m_dwt_setup(): DWT dwtcr 0x40000000, comp 4, watch/trigger
Info : 311 100 cortex_m.c:2042 cortex_m_examine(): STM32L433CCTx.cpu: hardware has 6 breakpoints, 4 watchpoints
Debug: 312 100 target.c:1501 target_call_event_callbacks(): target event 22 (examine-end)
Debug: 313 100 target.c:4256 target_handle_event(): target: (0) STM32L433CCTx.cpu (hla_target) event: 22 (examine-end) action:
# DBGMCU_CR |= DBG_STANDBY | DBG_STOP | DBG_SLEEP
mmw 0xE0042004 0x00000007 0
# Stop watchdog counters during halt
# DBGMCU_APB1_FZ |= DBG_IWDG_STOP | DBG_WWDG_STOP
mmw 0xE0042008 0x00001800 0
Debug: 314 100 hla_target.c:752 adapter_read_memory(): adapter_read_memory 0xe0042004 4 1
Debug: 315 104 command.c:145 script_debug(): command - ocd_command ocd_command type ocd_mww 0xE0042004 7
Debug: 316 104 command.c:145 script_debug(): command - mww ocd_mww 0xE0042004 7
Debug: 318 106 hla_target.c:766 adapter_write_memory(): adapter_write_memory 0xe0042004 4 1
Debug: 319 110 hla_target.c:752 adapter_read_memory(): adapter_read_memory 0xe0042008 4 1
Debug: 320 114 command.c:145 script_debug(): command - ocd_command ocd_command type ocd_mww 0xE0042008 6144
Debug: 321 114 command.c:145 script_debug(): command - mww ocd_mww 0xE0042008 6144
Debug: 323 116 hla_target.c:766 adapter_write_memory(): adapter_write_memory 0xe0042008 4 1
Debug: 324 120 command.c:145 script_debug(): command - ocd_command ocd_command type ocd_flash init
Debug: 325 120 command.c:145 script_debug(): command - ocd_flash ocd_flash init
Debug: 327 122 tcl.c:1097 handle_flash_init_command(): Initializing flash devices...
Debug: 328 122 command.c:366 register_command_handler(): registering 'ocd_flash'...
Debug: 329 122 command.c:366 register_command_handler(): registering 'ocd_flash'...
Debug: 330 122 command.c:366 register_command_handler(): registering 'ocd_flash'...
Debug: 331 122 command.c:366 register_command_handler(): registering 'ocd_flash'...
Debug: 332 122 command.c:366 register_command_handler(): registering 'ocd_flash'...
Debug: 333 122 command.c:366 register_command_handler(): registering 'ocd_flash'...
Debug: 334 122 command.c:366 register_command_handler(): registering 'ocd_flash'...
Debug: 335 122 command.c:366 register_command_handler(): registering 'ocd_flash'...
Debug: 336 122 command.c:366 register_command_handler(): registering 'ocd_flash'...
Debug: 337 122 command.c:366 register_command_handler(): registering 'ocd_flash'...
Debug: 338 122 command.c:366 register_command_handler(): registering 'ocd_flash'...
Debug: 339 122 command.c:366 register_command_handler(): registering 'ocd_flash'...
Debug: 340 122 command.c:366 register_command_handler(): registering 'ocd_flash'...
Debug: 341 122 command.c:366 register_command_handler(): registering 'ocd_flash'...
Debug: 342 122 command.c:366 register_command_handler(): registering 'ocd_flash'...
Debug: 343 122 command.c:145 script_debug(): command - ocd_command ocd_command type ocd_mflash init
Debug: 344 122 command.c:145 script_debug(): command - ocd_mflash ocd_mflash init
Debug: 346 124 mflash.c:1379 handle_mflash_init_command(): Initializing mflash devices...
Debug: 347 124 command.c:145 script_debug(): command - ocd_command ocd_command type ocd_nand init
Debug: 348 124 command.c:145 script_debug(): command - ocd_nand ocd_nand init
Debug: 350 126 tcl.c:497 handle_nand_init_command(): Initializing NAND devices...
Debug: 351 126 command.c:145 script_debug(): command - ocd_command ocd_command type ocd_pld init
Debug: 352 126 command.c:145 script_debug(): command - ocd_pld ocd_pld init
Debug: 354 128 pld.c:207 handle_pld_init_command(): Initializing PLDs...
### Start of Telnet Session here
Info : 355 52386 server.c:91 add_connection(): accepting 'telnet' connection on tcp/4444
Debug: 356 63857 command.c:145 script_debug(): command - ocd_command ocd_command type ocd_reset halt
Debug: 357 63857 command.c:145 script_debug(): command - reset ocd_reset halt
Debug: 359 63859 target.c:1519 target_call_reset_callbacks(): target reset 2 (halt)
Debug: 360 63859 command.c:145 script_debug(): command - ocd_command ocd_command type ocd_target names
Debug: 361 63859 command.c:145 script_debug(): command - ocd_target ocd_target names
Debug: 362 63859 command.c:145 script_debug(): command - ocd_command ocd_command type ocd_STM32L433CCTx.cpu invoke-event reset-start
Debug: 363 63859 command.c:145 script_debug(): command - ocd_STM32L433CCTx.cpu ocd_STM32L433CCTx.cpu invoke-event reset-start
Debug: 364 63859 command.c:145 script_debug(): command - ocd_command ocd_command type ocd_transport select
Debug: 365 63859 command.c:145 script_debug(): command - ocd_transport ocd_transport select
Debug: 366 63859 command.c:145 script_debug(): command - ocd_command ocd_command type ocd_transport select
Debug: 367 63859 command.c:145 script_debug(): command - ocd_transport ocd_transport select
Debug: 368 63860 command.c:145 script_debug(): command - ocd_command ocd_command type ocd_STM32L433CCTx.cpu invoke-event examine-start
Debug: 369 63860 command.c:145 script_debug(): command - ocd_STM32L433CCTx.cpu ocd_STM32L433CCTx.cpu invoke-event examine-start
Debug: 370 63860 command.c:145 script_debug(): command - ocd_command ocd_command type ocd_STM32L433CCTx.cpu arp_examine
Debug: 371 63860 command.c:145 script_debug(): command - ocd_STM32L433CCTx.cpu ocd_STM32L433CCTx.cpu arp_examine
Debug: 372 63860 command.c:145 script_debug(): command - ocd_command ocd_command type ocd_STM32L433CCTx.cpu invoke-event examine-end
Debug: 373 63860 command.c:145 script_debug(): command - ocd_STM32L433CCTx.cpu ocd_STM32L433CCTx.cpu invoke-event examine-end
Debug: 374 63860 target.c:4256 target_handle_event(): target: (0) STM32L433CCTx.cpu (hla_target) event: 22 (examine-end) action:
# DBGMCU_CR |= DBG_STANDBY | DBG_STOP | DBG_SLEEP
mmw 0xE0042004 0x00000007 0
# Stop watchdog counters during halt
# DBGMCU_APB1_FZ |= DBG_IWDG_STOP | DBG_WWDG_STOP
mmw 0xE0042008 0x00001800 0
Debug: 375 63860 hla_target.c:752 adapter_read_memory(): adapter_read_memory 0xe0042004 4 1
Debug: 376 63863 command.c:145 script_debug(): command - ocd_command ocd_command type ocd_mww 0xE0042004 7
Debug: 377 63863 command.c:145 script_debug(): command - mww ocd_mww 0xE0042004 7
Debug: 379 63864 hla_target.c:766 adapter_write_memory(): adapter_write_memory 0xe0042004 4 1
Debug: 380 63867 hla_target.c:752 adapter_read_memory(): adapter_read_memory 0xe0042008 4 1
Debug: 381 63871 command.c:145 script_debug(): command - ocd_command ocd_command type ocd_mww 0xE0042008 6144
Debug: 382 63871 command.c:145 script_debug(): command - mww ocd_mww 0xE0042008 6144
Debug: 384 63871 hla_target.c:766 adapter_write_memory(): adapter_write_memory 0xe0042008 4 1
Debug: 385 63875 command.c:145 script_debug(): command - ocd_command ocd_command type ocd_STM32L433CCTx.cpu invoke-event reset-assert-pre
Debug: 386 63875 command.c:145 script_debug(): command - ocd_STM32L433CCTx.cpu ocd_STM32L433CCTx.cpu invoke-event reset-assert-pre
Debug: 387 63875 command.c:145 script_debug(): command - ocd_command ocd_command type ocd_transport select
Debug: 388 63875 command.c:145 script_debug(): command - ocd_transport ocd_transport select
Debug: 389 63875 command.c:145 script_debug(): command - ocd_command ocd_command type ocd_STM32L433CCTx.cpu arp_reset assert 1
Debug: 390 63875 command.c:145 script_debug(): command - ocd_STM32L433CCTx.cpu ocd_STM32L433CCTx.cpu arp_reset assert 1
Debug: 391 63875 target.c:1883 target_free_all_working_areas_restore(): freeing all working areas
Debug: 392 63875 hla_target.c:485 adapter_assert_reset(): adapter_assert_reset
Debug: 393 63883 command.c:145 script_debug(): command - ocd_command ocd_command type ocd_STM32L433CCTx.cpu invoke-event reset-assert-post
Debug: 394 63883 command.c:145 script_debug(): command - ocd_STM32L433CCTx.cpu ocd_STM32L433CCTx.cpu invoke-event reset-assert-post
Debug: 395 63883 command.c:145 script_debug(): command - ocd_command ocd_command type ocd_STM32L433CCTx.cpu invoke-event reset-deassert-pre
Debug: 396 63883 command.c:145 script_debug(): command - ocd_STM32L433CCTx.cpu ocd_STM32L433CCTx.cpu invoke-event reset-deassert-pre
Debug: 397 63883 command.c:145 script_debug(): command - ocd_command ocd_command type ocd_transport select
Debug: 398 63883 command.c:145 script_debug(): command - ocd_transport ocd_transport select
Debug: 399 63883 command.c:145 script_debug(): command - ocd_command ocd_command type ocd_STM32L433CCTx.cpu arp_reset deassert 1
Debug: 400 63883 command.c:145 script_debug(): command - ocd_STM32L433CCTx.cpu ocd_STM32L433CCTx.cpu arp_reset deassert 1
Debug: 401 63883 target.c:1883 target_free_all_working_areas_restore(): freeing all working areas
Debug: 402 63883 hla_target.c:548 adapter_deassert_reset(): adapter_deassert_reset
Debug: 403 63883 hla_interface.c:129 hl_interface_execute_queue(): hl_interface_execute_queue: ignored
Error: 404 63883 core.c:718 jtag_add_reset(): TRST/SRST error
Debug: 405 63884 command.c:145 script_debug(): command - ocd_command ocd_command type ocd_STM32L433CCTx.cpu invoke-event reset-deassert-post
Debug: 406 63884 command.c:145 script_debug(): command - ocd_STM32L433CCTx.cpu ocd_STM32L433CCTx.cpu invoke-event reset-deassert-post
Debug: 407 63884 command.c:145 script_debug(): command - ocd_command ocd_command type ocd_transport select
Debug: 408 63884 command.c:145 script_debug(): command - ocd_transport ocd_transport select
Debug: 409 63884 command.c:145 script_debug(): command - ocd_command ocd_command type ocd_STM32L433CCTx.cpu arp_waitstate halted 1000
Debug: 410 63884 command.c:145 script_debug(): command - ocd_STM32L433CCTx.cpu ocd_STM32L433CCTx.cpu arp_waitstate halted 1000
Debug: 411 63885 hla_target.c:752 adapter_read_memory(): adapter_read_memory 0xe000edf8 4 1
Debug: 412 63889 target.c:2226 target_read_u32(): address: 0xe000edf8, value: 0x00000000
Debug: 413 63889 hla_target.c:60 adapter_load_core_reg_u32(): adapter_load_core_reg_u32
Debug: 414 63891 hla_target.c:75 adapter_load_core_reg_u32(): load from core reg 0 value 0x0
Debug: 415 63891 hla_target.c:60 adapter_load_core_reg_u32(): adapter_load_core_reg_u32
Debug: 416 63893 hla_target.c:75 adapter_load_core_reg_u32(): load from core reg 1 value 0x0
Debug: 417 63893 hla_target.c:60 adapter_load_core_reg_u32(): adapter_load_core_reg_u32
Debug: 418 63895 hla_target.c:75 adapter_load_core_reg_u32(): load from core reg 2 value 0x0
Debug: 419 63895 hla_target.c:60 adapter_load_core_reg_u32(): adapter_load_core_reg_u32
Debug: 420 63897 hla_target.c:75 adapter_load_core_reg_u32(): load from core reg 3 value 0x0
Debug: 421 63897 hla_target.c:60 adapter_load_core_reg_u32(): adapter_load_core_reg_u32
Debug: 422 63899 hla_target.c:75 adapter_load_core_reg_u32(): load from core reg 4 value 0x0
Debug: 423 63899 hla_target.c:60 adapter_load_core_reg_u32(): adapter_load_core_reg_u32
Debug: 424 63901 hla_target.c:75 adapter_load_core_reg_u32(): load from core reg 5 value 0x0
Debug: 425 63901 hla_target.c:60 adapter_load_core_reg_u32(): adapter_load_core_reg_u32
Debug: 426 63903 hla_target.c:75 adapter_load_core_reg_u32(): load from core reg 6 value 0x0
Debug: 427 63903 hla_target.c:60 adapter_load_core_reg_u32(): adapter_load_core_reg_u32
Debug: 428 63905 hla_target.c:75 adapter_load_core_reg_u32(): load from core reg 7 value 0x0
Debug: 429 63905 hla_target.c:60 adapter_load_core_reg_u32(): adapter_load_core_reg_u32
Debug: 430 63907 hla_target.c:75 adapter_load_core_reg_u32(): load from core reg 8 value 0x0
Debug: 431 63907 hla_target.c:60 adapter_load_core_reg_u32(): adapter_load_core_reg_u32
Debug: 432 63909 hla_target.c:75 adapter_load_core_reg_u32(): load from core reg 9 value 0x0
Debug: 433 63909 hla_target.c:60 adapter_load_core_reg_u32(): adapter_load_core_reg_u32
Debug: 434 63911 hla_target.c:75 adapter_load_core_reg_u32(): load from core reg 10 value 0x0
Debug: 435 63911 hla_target.c:60 adapter_load_core_reg_u32(): adapter_load_core_reg_u32
Debug: 436 63913 hla_target.c:75 adapter_load_core_reg_u32(): load from core reg 11 value 0x0
Debug: 437 63913 hla_target.c:60 adapter_load_core_reg_u32(): adapter_load_core_reg_u32
Debug: 438 63915 hla_target.c:75 adapter_load_core_reg_u32(): load from core reg 12 value 0x0
Debug: 439 63915 hla_target.c:60 adapter_load_core_reg_u32(): adapter_load_core_reg_u32
Debug: 440 63917 hla_target.c:75 adapter_load_core_reg_u32(): load from core reg 13 value 0x20002c20
Debug: 441 63917 hla_target.c:60 adapter_load_core_reg_u32(): adapter_load_core_reg_u32
Debug: 442 63919 hla_target.c:75 adapter_load_core_reg_u32(): load from core reg 14 value 0xffffffff
Debug: 443 63919 hla_target.c:60 adapter_load_core_reg_u32(): adapter_load_core_reg_u32
Debug: 444 63921 hla_target.c:75 adapter_load_core_reg_u32(): load from core reg 15 value 0x1fff3f36
Debug: 445 63921 hla_target.c:60 adapter_load_core_reg_u32(): adapter_load_core_reg_u32
Debug: 446 63923 hla_target.c:75 adapter_load_core_reg_u32(): load from core reg 16 value 0x1000000
Debug: 447 63923 hla_target.c:60 adapter_load_core_reg_u32(): adapter_load_core_reg_u32
Debug: 448 63925 hla_target.c:75 adapter_load_core_reg_u32(): load from core reg 17 value 0x20002c20
Debug: 449 63925 hla_target.c:60 adapter_load_core_reg_u32(): adapter_load_core_reg_u32
Debug: 450 63927 hla_target.c:75 adapter_load_core_reg_u32(): load from core reg 18 value 0x0
Debug: 451 63927 hla_target.c:60 adapter_load_core_reg_u32(): adapter_load_core_reg_u32
Debug: 452 63929 hla_target.c:132 adapter_load_core_reg_u32(): load from special reg 19 value 0x0
Debug: 453 63929 hla_target.c:60 adapter_load_core_reg_u32(): adapter_load_core_reg_u32
Debug: 454 63931 hla_target.c:132 adapter_load_core_reg_u32(): load from special reg 20 value 0x0
Debug: 455 63931 hla_target.c:60 adapter_load_core_reg_u32(): adapter_load_core_reg_u32
Debug: 456 63933 hla_target.c:132 adapter_load_core_reg_u32(): load from special reg 21 value 0x0
Debug: 457 63933 hla_target.c:60 adapter_load_core_reg_u32(): adapter_load_core_reg_u32
Debug: 458 63935 hla_target.c:132 adapter_load_core_reg_u32(): load from special reg 22 value 0x0
Debug: 459 63935 hla_target.c:60 adapter_load_core_reg_u32(): adapter_load_core_reg_u32
Debug: 460 63935 target.c:2314 target_write_u32(): address: 0xe000edf4, value: 0x00000040
Debug: 461 63935 hla_target.c:766 adapter_write_memory(): adapter_write_memory 0xe000edf4 4 1
Debug: 462 63939 hla_target.c:752 adapter_read_memory(): adapter_read_memory 0xe000edf8 4 1
Debug: 463 63943 target.c:2226 target_read_u32(): address: 0xe000edf8, value: 0x00000000
Debug: 464 63943 hla_target.c:98 adapter_load_core_reg_u32(): load from FPU reg S0 value 0x0
Debug: 465 63943 hla_target.c:60 adapter_load_core_reg_u32(): adapter_load_core_reg_u32
Debug: 466 63943 target.c:2314 target_write_u32(): address: 0xe000edf4, value: 0x00000041
Debug: 467 63943 hla_target.c:766 adapter_write_memory(): adapter_write_memory 0xe000edf4 4 1
Debug: 468 63947 hla_target.c:752 adapter_read_memory(): adapter_read_memory 0xe000edf8 4 1
Debug: 469 63951 target.c:2226 target_read_u32(): address: 0xe000edf8, value: 0x00000000
Debug: 470 63951 hla_target.c:98 adapter_load_core_reg_u32(): load from FPU reg S1 value 0x0
Debug: 471 63951 hla_target.c:60 adapter_load_core_reg_u32(): adapter_load_core_reg_u32
Debug: 472 63951 target.c:2314 target_write_u32(): address: 0xe000edf4, value: 0x00000042
Debug: 473 63951 hla_target.c:766 adapter_write_memory(): adapter_write_memory 0xe000edf4 4 1
Debug: 474 63955 hla_target.c:752 adapter_read_memory(): adapter_read_memory 0xe000edf8 4 1
Debug: 475 63959 target.c:2226 target_read_u32(): address: 0xe000edf8, value: 0x00000000
Debug: 476 63959 hla_target.c:98 adapter_load_core_reg_u32(): load from FPU reg S2 value 0x0
Debug: 477 63959 hla_target.c:60 adapter_load_core_reg_u32(): adapter_load_core_reg_u32
Debug: 478 63959 target.c:2314 target_write_u32(): address: 0xe000edf4, value: 0x00000043
Debug: 479 63959 hla_target.c:766 adapter_write_memory(): adapter_write_memory 0xe000edf4 4 1
Debug: 480 63963 hla_target.c:752 adapter_read_memory(): adapter_read_memory 0xe000edf8 4 1
Debug: 481 63967 target.c:2226 target_read_u32(): address: 0xe000edf8, value: 0x00000000
Debug: 482 63967 hla_target.c:98 adapter_load_core_reg_u32(): load from FPU reg S3 value 0x0
Debug: 483 63967 hla_target.c:60 adapter_load_core_reg_u32(): adapter_load_core_reg_u32
Debug: 484 63967 target.c:2314 target_write_u32(): address: 0xe000edf4, value: 0x00000044
Debug: 485 63967 hla_target.c:766 adapter_write_memory(): adapter_write_memory 0xe000edf4 4 1
Debug: 486 63971 hla_target.c:752 adapter_read_memory(): adapter_read_memory 0xe000edf8 4 1
Debug: 487 63975 target.c:2226 target_read_u32(): address: 0xe000edf8, value: 0x00000000
Debug: 488 63975 hla_target.c:98 adapter_load_core_reg_u32(): load from FPU reg S4 value 0x0
Debug: 489 63975 hla_target.c:60 adapter_load_core_reg_u32(): adapter_load_core_reg_u32
Debug: 490 63975 target.c:2314 target_write_u32(): address: 0xe000edf4, value: 0x00000045
Debug: 491 63975 hla_target.c:766 adapter_write_memory(): adapter_write_memory 0xe000edf4 4 1
Debug: 492 63979 hla_target.c:752 adapter_read_memory(): adapter_read_memory 0xe000edf8 4 1
Debug: 493 63983 target.c:2226 target_read_u32(): address: 0xe000edf8, value: 0x00000000
Debug: 494 63983 hla_target.c:98 adapter_load_core_reg_u32(): load from FPU reg S5 value 0x0
Debug: 495 63983 hla_target.c:60 adapter_load_core_reg_u32(): adapter_load_core_reg_u32
Debug: 496 63983 target.c:2314 target_write_u32(): address: 0xe000edf4, value: 0x00000046
Debug: 497 63983 hla_target.c:766 adapter_write_memory(): adapter_write_memory 0xe000edf4 4 1
Debug: 498 63987 hla_target.c:752 adapter_read_memory(): adapter_read_memory 0xe000edf8 4 1
Debug: 499 63991 target.c:2226 target_read_u32(): address: 0xe000edf8, value: 0x00000000
Debug: 500 63991 hla_target.c:98 adapter_load_core_reg_u32(): load from FPU reg S6 value 0x0
Debug: 501 63991 hla_target.c:60 adapter_load_core_reg_u32(): adapter_load_core_reg_u32
Debug: 502 63991 target.c:2314 target_write_u32(): address: 0xe000edf4, value: 0x00000047
Debug: 503 63991 hla_target.c:766 adapter_write_memory(): adapter_write_memory 0xe000edf4 4 1
Debug: 504 63995 hla_target.c:752 adapter_read_memory(): adapter_read_memory 0xe000edf8 4 1
Debug: 505 63999 target.c:2226 target_read_u32(): address: 0xe000edf8, value: 0x00000000
Debug: 506 63999 hla_target.c:98 adapter_load_core_reg_u32(): load from FPU reg S7 value 0x0
Debug: 507 63999 hla_target.c:60 adapter_load_core_reg_u32(): adapter_load_core_reg_u32
Debug: 508 63999 target.c:2314 target_write_u32(): address: 0xe000edf4, value: 0x00000048
Debug: 509 63999 hla_target.c:766 adapter_write_memory(): adapter_write_memory 0xe000edf4 4 1
Debug: 510 64003 hla_target.c:752 adapter_read_memory(): adapter_read_memory 0xe000edf8 4 1
Debug: 511 64007 target.c:2226 target_read_u32(): address: 0xe000edf8, value: 0x00000000
Debug: 512 64007 hla_target.c:98 adapter_load_core_reg_u32(): load from FPU reg S8 value 0x0
Debug: 513 64007 hla_target.c:60 adapter_load_core_reg_u32(): adapter_load_core_reg_u32
Debug: 514 64007 target.c:2314 target_write_u32(): address: 0xe000edf4, value: 0x00000049
Debug: 515 64007 hla_target.c:766 adapter_write_memory(): adapter_write_memory 0xe000edf4 4 1
Debug: 516 64011 hla_target.c:752 adapter_read_memory(): adapter_read_memory 0xe000edf8 4 1
Debug: 517 64015 target.c:2226 target_read_u32(): address: 0xe000edf8, value: 0x00000000
Debug: 518 64015 hla_target.c:98 adapter_load_core_reg_u32(): load from FPU reg S9 value 0x0
Debug: 519 64015 hla_target.c:60 adapter_load_core_reg_u32(): adapter_load_core_reg_u32
Debug: 520 64015 target.c:2314 target_write_u32(): address: 0xe000edf4, value: 0x0000004a
Debug: 521 64015 hla_target.c:766 adapter_write_memory(): adapter_write_memory 0xe000edf4 4 1
Debug: 522 64019 hla_target.c:752 adapter_read_memory(): adapter_read_memory 0xe000edf8 4 1
Debug: 523 64022 target.c:2226 target_read_u32(): address: 0xe000edf8, value: 0x00000000
Debug: 524 64022 hla_target.c:98 adapter_load_core_reg_u32(): load from FPU reg S10 value 0x0
Debug: 525 64022 hla_target.c:60 adapter_load_core_reg_u32(): adapter_load_core_reg_u32
Debug: 526 64022 target.c:2314 target_write_u32(): address: 0xe000edf4, value: 0x0000004b
Debug: 527 64022 hla_target.c:766 adapter_write_memory(): adapter_write_memory 0xe000edf4 4 1
Debug: 528 64026 hla_target.c:752 adapter_read_memory(): adapter_read_memory 0xe000edf8 4 1
Debug: 529 64030 target.c:2226 target_read_u32(): address: 0xe000edf8, value: 0x00000000
Debug: 530 64030 hla_target.c:98 adapter_load_core_reg_u32(): load from FPU reg S11 value 0x0
Debug: 531 64030 hla_target.c:60 adapter_load_core_reg_u32(): adapter_load_core_reg_u32
Debug: 532 64030 target.c:2314 target_write_u32(): address: 0xe000edf4, value: 0x0000004c
Debug: 533 64030 hla_target.c:766 adapter_write_memory(): adapter_write_memory 0xe000edf4 4 1
Debug: 534 64034 hla_target.c:752 adapter_read_memory(): adapter_read_memory 0xe000edf8 4 1
Debug: 535 64038 target.c:2226 target_read_u32(): address: 0xe000edf8, value: 0x00000000
Debug: 536 64038 hla_target.c:98 adapter_load_core_reg_u32(): load from FPU reg S12 value 0x0
Debug: 537 64038 hla_target.c:60 adapter_load_core_reg_u32(): adapter_load_core_reg_u32
Debug: 538 64038 target.c:2314 target_write_u32(): address: 0xe000edf4, value: 0x0000004d
Debug: 539 64038 hla_target.c:766 adapter_write_memory(): adapter_write_memory 0xe000edf4 4 1
Debug: 540 64042 hla_target.c:752 adapter_read_memory(): adapter_read_memory 0xe000edf8 4 1
Debug: 541 64046 target.c:2226 target_read_u32(): address: 0xe000edf8, value: 0x00000000
Debug: 542 64046 hla_target.c:98 adapter_load_core_reg_u32(): load from FPU reg S13 value 0x0
Debug: 543 64046 hla_target.c:60 adapter_load_core_reg_u32(): adapter_load_core_reg_u32
Debug: 544 64046 target.c:2314 target_write_u32(): address: 0xe000edf4, value: 0x0000004e
Debug: 545 64046 hla_target.c:766 adapter_write_memory(): adapter_write_memory 0xe000edf4 4 1
Debug: 546 64050 hla_target.c:752 adapter_read_memory(): adapter_read_memory 0xe000edf8 4 1
Debug: 547 64054 target.c:2226 target_read_u32(): address: 0xe000edf8, value: 0x00000000
Debug: 548 64054 hla_target.c:98 adapter_load_core_reg_u32(): load from FPU reg S14 value 0x0
Debug: 549 64054 hla_target.c:60 adapter_load_core_reg_u32(): adapter_load_core_reg_u32
Debug: 550 64054 target.c:2314 target_write_u32(): address: 0xe000edf4, value: 0x0000004f
Debug: 551 64054 hla_target.c:766 adapter_write_memory(): adapter_write_memory 0xe000edf4 4 1
Debug: 552 64058 hla_target.c:752 adapter_read_memory(): adapter_read_memory 0xe000edf8 4 1
Debug: 553 64062 target.c:2226 target_read_u32(): address: 0xe000edf8, value: 0x00000000
Debug: 554 64062 hla_target.c:98 adapter_load_core_reg_u32(): load from FPU reg S15 value 0x0
Debug: 555 64062 hla_target.c:60 adapter_load_core_reg_u32(): adapter_load_core_reg_u32
Debug: 556 64062 target.c:2314 target_write_u32(): address: 0xe000edf4, value: 0x00000050
Debug: 557 64062 hla_target.c:766 adapter_write_memory(): adapter_write_memory 0xe000edf4 4 1
Debug: 558 64066 hla_target.c:752 adapter_read_memory(): adapter_read_memory 0xe000edf8 4 1
Debug: 559 64070 target.c:2226 target_read_u32(): address: 0xe000edf8, value: 0x00000000
Debug: 560 64070 hla_target.c:98 adapter_load_core_reg_u32(): load from FPU reg S16 value 0x0
Debug: 561 64070 hla_target.c:60 adapter_load_core_reg_u32(): adapter_load_core_reg_u32
Debug: 562 64070 target.c:2314 target_write_u32(): address: 0xe000edf4, value: 0x00000051
Debug: 563 64070 hla_target.c:766 adapter_write_memory(): adapter_write_memory 0xe000edf4 4 1
Debug: 564 64074 hla_target.c:752 adapter_read_memory(): adapter_read_memory 0xe000edf8 4 1
Debug: 565 64078 target.c:2226 target_read_u32(): address: 0xe000edf8, value: 0x00000000
Debug: 566 64078 hla_target.c:98 adapter_load_core_reg_u32(): load from FPU reg S17 value 0x0
Debug: 567 64078 hla_target.c:60 adapter_load_core_reg_u32(): adapter_load_core_reg_u32
Debug: 568 64078 target.c:2314 target_write_u32(): address: 0xe000edf4, value: 0x00000052
Debug: 569 64078 hla_target.c:766 adapter_write_memory(): adapter_write_memory 0xe000edf4 4 1
Debug: 570 64082 hla_target.c:752 adapter_read_memory(): adapter_read_memory 0xe000edf8 4 1
Debug: 571 64086 target.c:2226 target_read_u32(): address: 0xe000edf8, value: 0x00000000
Debug: 572 64086 hla_target.c:98 adapter_load_core_reg_u32(): load from FPU reg S18 value 0x0
Debug: 573 64086 hla_target.c:60 adapter_load_core_reg_u32(): adapter_load_core_reg_u32
Debug: 574 64086 target.c:2314 target_write_u32(): address: 0xe000edf4, value: 0x00000053
Debug: 575 64086 hla_target.c:766 adapter_write_memory(): adapter_write_memory 0xe000edf4 4 1
Debug: 576 64090 hla_target.c:752 adapter_read_memory(): adapter_read_memory 0xe000edf8 4 1
Debug: 577 64094 target.c:2226 target_read_u32(): address: 0xe000edf8, value: 0x00000000
Debug: 578 64094 hla_target.c:98 adapter_load_core_reg_u32(): load from FPU reg S19 value 0x0
Debug: 579 64094 hla_target.c:60 adapter_load_core_reg_u32(): adapter_load_core_reg_u32
Debug: 580 64094 target.c:2314 target_write_u32(): address: 0xe000edf4, value: 0x00000054
Debug: 581 64094 hla_target.c:766 adapter_write_memory(): adapter_write_memory 0xe000edf4 4 1
Debug: 582 64098 hla_target.c:752 adapter_read_memory(): adapter_read_memory 0xe000edf8 4 1
Debug: 583 64102 target.c:2226 target_read_u32(): address: 0xe000edf8, value: 0x00000000
Debug: 584 64102 hla_target.c:98 adapter_load_core_reg_u32(): load from FPU reg S20 value 0x0
Debug: 585 64102 hla_target.c:60 adapter_load_core_reg_u32(): adapter_load_core_reg_u32
Debug: 586 64102 target.c:2314 target_write_u32(): address: 0xe000edf4, value: 0x00000055
Debug: 587 64102 hla_target.c:766 adapter_write_memory(): adapter_write_memory 0xe000edf4 4 1
Debug: 588 64106 hla_target.c:752 adapter_read_memory(): adapter_read_memory 0xe000edf8 4 1
Debug: 589 64110 target.c:2226 target_read_u32(): address: 0xe000edf8, value: 0x00000000
Debug: 590 64110 hla_target.c:98 adapter_load_core_reg_u32(): load from FPU reg S21 value 0x0
Debug: 591 64110 hla_target.c:60 adapter_load_core_reg_u32(): adapter_load_core_reg_u32
Debug: 592 64110 target.c:2314 target_write_u32(): address: 0xe000edf4, value: 0x00000056
Debug: 593 64110 hla_target.c:766 adapter_write_memory(): adapter_write_memory 0xe000edf4 4 1
Debug: 594 64114 hla_target.c:752 adapter_read_memory(): adapter_read_memory 0xe000edf8 4 1
Debug: 595 64118 target.c:2226 target_read_u32(): address: 0xe000edf8, value: 0x00000000
Debug: 596 64118 hla_target.c:98 adapter_load_core_reg_u32(): load from FPU reg S22 value 0x0
Debug: 597 64118 hla_target.c:60 adapter_load_core_reg_u32(): adapter_load_core_reg_u32
Debug: 598 64118 target.c:2314 target_write_u32(): address: 0xe000edf4, value: 0x00000057
Debug: 599 64118 hla_target.c:766 adapter_write_memory(): adapter_write_memory 0xe000edf4 4 1
Debug: 600 64122 hla_target.c:752 adapter_read_memory(): adapter_read_memory 0xe000edf8 4 1
Debug: 601 64126 target.c:2226 target_read_u32(): address: 0xe000edf8, value: 0x00000000
Debug: 602 64126 hla_target.c:98 adapter_load_core_reg_u32(): load from FPU reg S23 value 0x0
Debug: 603 64126 hla_target.c:60 adapter_load_core_reg_u32(): adapter_load_core_reg_u32
Debug: 604 64126 target.c:2314 target_write_u32(): address: 0xe000edf4, value: 0x00000058
Debug: 605 64126 hla_target.c:766 adapter_write_memory(): adapter_write_memory 0xe000edf4 4 1
Debug: 606 64130 hla_target.c:752 adapter_read_memory(): adapter_read_memory 0xe000edf8 4 1
Debug: 607 64134 target.c:2226 target_read_u32(): address: 0xe000edf8, value: 0x00000000
Debug: 608 64134 hla_target.c:98 adapter_load_core_reg_u32(): load from FPU reg S24 value 0x0
Debug: 609 64134 hla_target.c:60 adapter_load_core_reg_u32(): adapter_load_core_reg_u32
Debug: 610 64134 target.c:2314 target_write_u32(): address: 0xe000edf4, value: 0x00000059
Debug: 611 64134 hla_target.c:766 adapter_write_memory(): adapter_write_memory 0xe000edf4 4 1
Debug: 612 64138 hla_target.c:752 adapter_read_memory(): adapter_read_memory 0xe000edf8 4 1
Debug: 613 64142 target.c:2226 target_read_u32(): address: 0xe000edf8, value: 0x00000000
Debug: 614 64142 hla_target.c:98 adapter_load_core_reg_u32(): load from FPU reg S25 value 0x0
Debug: 615 64142 hla_target.c:60 adapter_load_core_reg_u32(): adapter_load_core_reg_u32
Debug: 616 64142 target.c:2314 target_write_u32(): address: 0xe000edf4, value: 0x0000005a
Debug: 617 64142 hla_target.c:766 adapter_write_memory(): adapter_write_memory 0xe000edf4 4 1
Debug: 618 64146 hla_target.c:752 adapter_read_memory(): adapter_read_memory 0xe000edf8 4 1
Debug: 619 64150 target.c:2226 target_read_u32(): address: 0xe000edf8, value: 0x00000000
Debug: 620 64150 hla_target.c:98 adapter_load_core_reg_u32(): load from FPU reg S26 value 0x0
Debug: 621 64150 hla_target.c:60 adapter_load_core_reg_u32(): adapter_load_core_reg_u32
Debug: 622 64150 target.c:2314 target_write_u32(): address: 0xe000edf4, value: 0x0000005b
Debug: 623 64150 hla_target.c:766 adapter_write_memory(): adapter_write_memory 0xe000edf4 4 1
Debug: 624 64154 hla_target.c:752 adapter_read_memory(): adapter_read_memory 0xe000edf8 4 1
Debug: 625 64158 target.c:2226 target_read_u32(): address: 0xe000edf8, value: 0x00000000
Debug: 626 64158 hla_target.c:98 adapter_load_core_reg_u32(): load from FPU reg S27 value 0x0
Debug: 627 64158 hla_target.c:60 adapter_load_core_reg_u32(): adapter_load_core_reg_u32
Debug: 628 64158 target.c:2314 target_write_u32(): address: 0xe000edf4, value: 0x0000005c
Debug: 629 64158 hla_target.c:766 adapter_write_memory(): adapter_write_memory 0xe000edf4 4 1
Debug: 630 64162 hla_target.c:752 adapter_read_memory(): adapter_read_memory 0xe000edf8 4 1
Debug: 631 64166 target.c:2226 target_read_u32(): address: 0xe000edf8, value: 0x00000000
Debug: 632 64166 hla_target.c:98 adapter_load_core_reg_u32(): load from FPU reg S28 value 0x0
Debug: 633 64166 hla_target.c:60 adapter_load_core_reg_u32(): adapter_load_core_reg_u32
Debug: 634 64166 target.c:2314 target_write_u32(): address: 0xe000edf4, value: 0x0000005d
Debug: 635 64166 hla_target.c:766 adapter_write_memory(): adapter_write_memory 0xe000edf4 4 1
Debug: 636 64170 hla_target.c:752 adapter_read_memory(): adapter_read_memory 0xe000edf8 4 1
Debug: 637 64174 target.c:2226 target_read_u32(): address: 0xe000edf8, value: 0x00000000
Debug: 638 64174 hla_target.c:98 adapter_load_core_reg_u32(): load from FPU reg S29 value 0x0
Debug: 639 64174 hla_target.c:60 adapter_load_core_reg_u32(): adapter_load_core_reg_u32
Debug: 640 64174 target.c:2314 target_write_u32(): address: 0xe000edf4, value: 0x0000005e
Debug: 641 64174 hla_target.c:766 adapter_write_memory(): adapter_write_memory 0xe000edf4 4 1
Debug: 642 64178 hla_target.c:752 adapter_read_memory(): adapter_read_memory 0xe000edf8 4 1
Debug: 643 64182 target.c:2226 target_read_u32(): address: 0xe000edf8, value: 0x00000000
Debug: 644 64182 hla_target.c:98 adapter_load_core_reg_u32(): load from FPU reg S30 value 0x0
Debug: 645 64182 hla_target.c:60 adapter_load_core_reg_u32(): adapter_load_core_reg_u32
Debug: 646 64182 target.c:2314 target_write_u32(): address: 0xe000edf4, value: 0x0000005f
Debug: 647 64182 hla_target.c:766 adapter_write_memory(): adapter_write_memory 0xe000edf4 4 1
Debug: 648 64186 hla_target.c:752 adapter_read_memory(): adapter_read_memory 0xe000edf8 4 1
Debug: 649 64190 target.c:2226 target_read_u32(): address: 0xe000edf8, value: 0x00000000
Debug: 650 64190 hla_target.c:98 adapter_load_core_reg_u32(): load from FPU reg S31 value 0x0
Debug: 651 64190 hla_target.c:60 adapter_load_core_reg_u32(): adapter_load_core_reg_u32
Debug: 652 64190 target.c:2314 target_write_u32(): address: 0xe000edf4, value: 0x00000021
Debug: 653 64190 hla_target.c:766 adapter_write_memory(): adapter_write_memory 0xe000edf4 4 1
Debug: 654 64194 hla_target.c:752 adapter_read_memory(): adapter_read_memory 0xe000edf8 4 1
Debug: 655 64198 target.c:2226 target_read_u32(): address: 0xe000edf8, value: 0x00000000
Debug: 656 64198 hla_target.c:86 adapter_load_core_reg_u32(): load from FPSCR value 0x0
Debug: 657 64200 hla_target.c:433 adapter_debug_entry(): entered debug state in core mode: Thread at PC 0x1fff3f36, target->state: halted
Debug: 658 64200 target.c:1501 target_call_event_callbacks(): target event 0 (gdb-halt)
Debug: 659 64200 target.c:1501 target_call_event_callbacks(): target event 1 (halted)
User : 660 64200 target.c:1936 target_arch_state(): STM32L433CCTx.cpu: target state: halted
User : 661 64200 armv7m.c:553 armv7m_arch_state(): target halted due to debug-request, current mode: Thread
xPSR: 0x01000000 pc: 0x1fff3f36 msp: 0x20002c20
Debug: 662 64200 hla_target.c:472 adapter_poll(): halted: PC: 0x1fff3f36
Debug: 663 64200 command.c:145 script_debug(): command - ocd_command ocd_command type ocd_STM32L433CCTx.cpu curstate
Debug: 664 64200 command.c:145 script_debug(): command - ocd_STM32L433CCTx.cpu ocd_STM32L433CCTx.cpu curstate
Debug: 665 64200 command.c:145 script_debug(): command - ocd_command ocd_command type ocd_STM32L433CCTx.cpu invoke-event reset-end
Debug: 666 64200 command.c:145 script_debug(): command - ocd_STM32L433CCTx.cpu ocd_STM32L433CCTx.cpu invoke-event reset-end
Debug: 667 78844 command.c:145 script_debug(): command - ocd_command ocd_command type ocd_stm32l4x mass_erase 0
Debug: 668 78844 command.c:145 script_debug(): command - ocd_stm32l4x ocd_stm32l4x mass_erase 0
Debug: 670 78846 hla_target.c:752 adapter_read_memory(): adapter_read_memory 0xe0042000 4 1
Debug: 671 78850 target.c:2226 target_read_u32(): address: 0xe0042000, value: 0x10016435
Info : 672 78850 stm32l4x.c:905 stm32x_probe(): Device id = 0x10016435
Debug: 673 78850 hla_target.c:752 adapter_read_memory(): adapter_read_memory 0x1fff75e0 2 1
Debug: 674 78854 target.c:2250 target_read_u16(): address: 0x1fff75e0, value: 0x0100
Info : 675 78854 stm32l4x.c:940 stm32x_probe(): STM32L4xx flash size is 256kb, base address is 0x8000000
Debug: 676 78854 hla_target.c:752 adapter_read_memory(): adapter_read_memory 0x40022014 4 1
Debug: 677 78858 target.c:2226 target_read_u32(): address: 0x40022014, value: 0xc0000000
Debug: 678 78858 target.c:2314 target_write_u32(): address: 0x40022008, value: 0x45670123
Debug: 679 78858 hla_target.c:766 adapter_write_memory(): adapter_write_memory 0x40022008 4 1
Debug: 680 78862 target.c:2314 target_write_u32(): address: 0x40022008, value: 0xcdef89ab
Debug: 681 78862 hla_target.c:766 adapter_write_memory(): adapter_write_memory 0x40022008 4 1
Debug: 682 78866 hla_target.c:752 adapter_read_memory(): adapter_read_memory 0x40022014 4 1
Debug: 683 78870 target.c:2226 target_read_u32(): address: 0x40022014, value: 0x40000000
Debug: 684 78870 hla_target.c:752 adapter_read_memory(): adapter_read_memory 0x40022010 4 1
Debug: 685 78874 target.c:2226 target_read_u32(): address: 0x40022010, value: 0x00020000
Debug: 686 78874 hla_target.c:752 adapter_read_memory(): adapter_read_memory 0x40022014 4 1
Debug: 687 78878 target.c:2226 target_read_u32(): address: 0x40022014, value: 0x40000000
Debug: 688 78878 target.c:2314 target_write_u32(): address: 0x40022014, value: 0x40000004
Debug: 689 78878 hla_target.c:766 adapter_write_memory(): adapter_write_memory 0x40022014 4 1
Debug: 690 78882 target.c:2314 target_write_u32(): address: 0x40022014, value: 0x40010004
Debug: 691 78882 hla_target.c:766 adapter_write_memory(): adapter_write_memory 0x40022014 4 1
Debug: 692 78886 hla_target.c:752 adapter_read_memory(): adapter_read_memory 0x40022010 4 1
Debug: 693 78890 target.c:2226 target_read_u32(): address: 0x40022010, value: 0x00030000
Debug: 694 78892 hla_target.c:752 adapter_read_memory(): adapter_read_memory 0x40022010 4 1
Debug: 695 78895 target.c:2226 target_read_u32(): address: 0x40022010, value: 0x00030000
Debug: 696 78897 hla_target.c:752 adapter_read_memory(): adapter_read_memory 0x40022010 4 1
Debug: 697 78900 target.c:2226 target_read_u32(): address: 0x40022010, value: 0x00030000
Debug: 698 78901 hla_target.c:752 adapter_read_memory(): adapter_read_memory 0x40022010 4 1
Debug: 699 78905 target.c:2226 target_read_u32(): address: 0x40022010, value: 0x00030000
Debug: 700 78907 hla_target.c:752 adapter_read_memory(): adapter_read_memory 0x40022010 4 1
Debug: 701 78910 target.c:2226 target_read_u32(): address: 0x40022010, value: 0x00020000
Debug: 702 78910 hla_target.c:752 adapter_read_memory(): adapter_read_memory 0x40022014 4 1
Debug: 703 78914 target.c:2226 target_read_u32(): address: 0x40022014, value: 0x40000004
Debug: 704 78914 target.c:2314 target_write_u32(): address: 0x40022014, value: 0xc0000004
Debug: 705 78914 hla_target.c:766 adapter_write_memory(): adapter_write_memory 0x40022014 4 1
User : 706 78918 command.c:546 command_print(): stm32l4x mass erase complete
Debug: 707 89892 command.c:145 script_debug(): command - ocd_command ocd_command type ocd_flash write_image /array_data01/STM32L433CCTx-mini-sys-01/L433CCTx-mini-sys/Debug/L433CCTx-mini-sys.elf
Debug: 708 89892 command.c:145 script_debug(): command - ocd_flash ocd_flash write_image /array_data01/STM32L433CCTx-mini-sys-01/L433CCTx-mini-sys/Debug/L433CCTx-mini-sys.elf
Debug: 710 89895 configuration.c:84 find_file(): found /array_data01/STM32L433CCTx-mini-sys-01/L433CCTx-mini-sys/Debug/L433CCTx-mini-sys.elf
Debug: 711 89895 image.c:71 autodetect_image_type(): ELF image detected.
Debug: 712 89895 configuration.c:84 find_file(): found /array_data01/STM32L433CCTx-mini-sys-01/L433CCTx-mini-sys/Debug/L433CCTx-mini-sys.elf
Debug: 713 89895 core.c:712 flash_write_unlock(): image_read_section: section = 0, t_section_num = 0, section_offset = 0, buffer_size = 0, size_read = 65864
Debug: 714 89895 image.c:480 image_elf_read_section(): load segment 0 at 0x0 (sz = 0x10148)
Debug: 715 89895 image.c:487 image_elf_read_section(): read elf: size = 0x65864 at 0x10000
Debug: 716 89895 core.c:712 flash_write_unlock(): image_read_section: section = 1, t_section_num = 1, section_offset = 0, buffer_size = 65864, size_read = 688
Debug: 717 89895 image.c:480 image_elf_read_section(): load segment 1 at 0x0 (sz = 0x2b0)
Debug: 718 89895 image.c:487 image_elf_read_section(): read elf: size = 0x688 at 0x30000
Debug: 719 89895 hla_target.c:752 adapter_read_memory(): adapter_read_memory 0x40022014 4 1
Debug: 720 89899 target.c:2226 target_read_u32(): address: 0x40022014, value: 0xc0000004
Debug: 721 89899 target.c:2314 target_write_u32(): address: 0x40022008, value: 0x45670123
Debug: 722 89899 hla_target.c:766 adapter_write_memory(): adapter_write_memory 0x40022008 4 1
Debug: 723 89903 target.c:2314 target_write_u32(): address: 0x40022008, value: 0xcdef89ab
Debug: 724 89903 hla_target.c:766 adapter_write_memory(): adapter_write_memory 0x40022008 4 1
Debug: 725 89907 hla_target.c:752 adapter_read_memory(): adapter_read_memory 0x40022014 4 1
Debug: 726 89911 target.c:2226 target_read_u32(): address: 0x40022014, value: 0x40000004
Debug: 727 89911 target.c:1708 target_alloc_working_area_try(): MMU disabled, using physical address for working memory 0x20000000
Debug: 728 89911 target.c:1761 target_alloc_working_area_try(): allocated new working area of 108 bytes at address 0x20000000
Debug: 729 89911 target.c:1624 print_wa_layout(): * 0x20000000-0x2000006b (108 bytes)
Debug: 730 89911 target.c:1624 print_wa_layout(): 0x2000006c-0x2000bfff (49044 bytes)
Debug: 731 89911 target.c:2017 target_write_buffer(): writing buffer of 106 byte at 0x20000000
Debug: 732 89911 hla_target.c:766 adapter_write_memory(): adapter_write_memory 0x20000000 4 26
Debug: 733 89916 hla_target.c:766 adapter_write_memory(): adapter_write_memory 0x20000068 2 1
Debug: 734 89920 target.c:1761 target_alloc_working_area_try(): allocated new working area of 16384 bytes at address 0x2000006c
Debug: 735 89920 target.c:1624 print_wa_layout(): * 0x20000000-0x2000006b (108 bytes)
Debug: 736 89920 target.c:1624 print_wa_layout(): * 0x2000006c-0x2000406b (16384 bytes)
Debug: 737 89920 target.c:1624 print_wa_layout(): 0x2000406c-0x2000bfff (32660 bytes)
Debug: 738 89920 target.c:2314 target_write_u32(): address: 0x2000006c, value: 0x20000074
Debug: 739 89920 hla_target.c:766 adapter_write_memory(): adapter_write_memory 0x2000006c 4 1
Debug: 740 89924 target.c:2314 target_write_u32(): address: 0x20000070, value: 0x20000074
Debug: 741 89924 hla_target.c:766 adapter_write_memory(): adapter_write_memory 0x20000070 4 1
Debug: 742 89928 target.c:1501 target_call_event_callbacks(): target event 3 (resume-start)
Debug: 743 89928 hla_target.c:600 adapter_resume(): adapter_resume 0 0x20000000 1 1
Debug: 744 89928 target.c:2314 target_write_u32(): address: 0xe000edfc, value: 0x01000000
Debug: 745 89928 hla_target.c:766 adapter_write_memory(): adapter_write_memory 0xe000edfc 4 1
Debug: 746 89932 armv7m.c:146 armv7m_restore_context():
Debug: 747 89932 armv7m.c:278 armv7m_write_core_reg(): write core reg 15 value 0x20000000
Debug: 748 89932 hla_target.c:150 adapter_store_core_reg_u32(): adapter_store_core_reg_u32
Debug: 749 89934 hla_target.c:168 adapter_store_core_reg_u32(): write core reg 15 value 0x20000000
Debug: 750 89934 armv7m.c:278 armv7m_write_core_reg(): write core reg 3 value 0x207f
Debug: 751 89934 hla_target.c:150 adapter_store_core_reg_u32(): adapter_store_core_reg_u32
Debug: 752 89936 hla_target.c:168 adapter_store_core_reg_u32(): write core reg 3 value 0x207f
Debug: 753 89936 armv7m.c:278 armv7m_write_core_reg(): write core reg 2 value 0x8000000
Debug: 754 89936 hla_target.c:150 adapter_store_core_reg_u32(): adapter_store_core_reg_u32
Debug: 755 89938 hla_target.c:168 adapter_store_core_reg_u32(): write core reg 2 value 0x8000000
Debug: 756 89938 armv7m.c:278 armv7m_write_core_reg(): write core reg 1 value 0x2000406c
Debug: 757 89938 hla_target.c:150 adapter_store_core_reg_u32(): adapter_store_core_reg_u32
Debug: 758 89940 hla_target.c:168 adapter_store_core_reg_u32(): write core reg 1 value 0x2000406c
Debug: 759 89940 armv7m.c:278 armv7m_write_core_reg(): write core reg 0 value 0x2000006c
Debug: 760 89940 hla_target.c:150 adapter_store_core_reg_u32(): adapter_store_core_reg_u32
Debug: 761 89942 hla_target.c:168 adapter_store_core_reg_u32(): write core reg 0 value 0x2000006c
Debug: 762 89942 target.c:2314 target_write_u32(): address: 0xe000edf8, value: 0x00000000
Debug: 763 89942 hla_target.c:766 adapter_write_memory(): adapter_write_memory 0xe000edf8 4 1
Debug: 764 89948 target.c:1501 target_call_event_callbacks(): target event 20 (debug-resumed)
Debug: 765 89948 target.c:1501 target_call_event_callbacks(): target event 4 (resume-end)
Debug: 766 89948 hla_target.c:752 adapter_read_memory(): adapter_read_memory 0x20000070 4 1
Debug: 767 89952 target.c:2226 target_read_u32(): address: 0x20000070, value: 0x20000074
Debug: 768 89952 target.c:936 target_run_flash_async_algorithm(): offs 0x0 count 0x207f wp 0x20000074 rp 0x20000074
Debug: 769 89952 target.c:2017 target_write_buffer(): writing buffer of 16368 byte at 0x20000074
Debug: 770 89952 hla_target.c:766 adapter_write_memory(): adapter_write_memory 0x20000074 4 4092
Debug: 771 90110 stlink_usb.c:461 stlink_usb_error_check(): SWD_AP_ERROR
Debug: 772 90110 target.c:2314 target_write_u32(): address: 0x2000006c, value: 0x00000000
Debug: 773 90110 hla_target.c:766 adapter_write_memory(): adapter_write_memory 0x2000006c 4 1
Debug: 774 90114 stlink_usb.c:461 stlink_usb_error_check(): SWD_AP_ERROR
Debug: 775 90114 target.c:2319 target_write_u32(): failed: -4
Debug: 776 90116 stlink_usb.c:461 stlink_usb_error_check(): SWD_AP_ERROR
Error: 777 90116 hla_target.c:448 adapter_poll(): jtag status contains invalid mode value - communication failure
Debug: 778 90116 hla_target.c:568 adapter_halt(): adapter_halt
Debug: 779 90118 stlink_usb.c:461 stlink_usb_error_check(): SWD_AP_ERROR
Error: 780 90118 target.c:1013 target_run_flash_async_algorithm(): error waiting for target flash write algorithm
Debug: 781 90118 target.c:1830 target_free_working_area_restore(): freed 16384 bytes of working area at address 0x2000006c
Debug: 782 90118 target.c:1624 print_wa_layout(): * 0x20000000-0x2000006b (108 bytes)
Debug: 783 90118 target.c:1624 print_wa_layout(): 0x2000006c-0x2000bfff (49044 bytes)
Debug: 784 90118 target.c:1830 target_free_working_area_restore(): freed 108 bytes of working area at address 0x20000000
Debug: 785 90118 target.c:1624 print_wa_layout(): 0x20000000-0x2000bfff (49152 bytes)
Error: 786 90118 core.c:93 flash_driver_write(): error writing to flash at address 0x08000000 at offset 0x00000000
Debug: 787 90118 command.c:628 run_command(): Command failed with error code -4
User : 788 90118 command.c:689 command_run_line():
Info : 789 90118 stlink_usb.c:1031 stlink_usb_state(): Previous state query failed, trying to reconnect
Debug: 790 95430 hla_interface.c:119 hl_interface_quit(): hl_interface_quit
Telnet to port 4444 output:
Open On-Chip Debugger > reset halt TRST/SRST error STM32L433CCTx.cpu: target state: halted target halted due to debug-request, current mode: Thread xPSR: 0x01000000 pc: 0x1fff3f36 msp: 0x20002c20 > stm32l4x mass_erase 0 Device id = 0x10016435 STM32L4xx flash size is 256kb, base address is 0x8000000 stm32l4x mass erase complete > flash write_image /array_data01/STM32L433CCTx-mini-sys-01/L433CCTx-mini-sys/Debug/L433CCTx-mini-sys.elf jtag status contains invalid mode value - communication failure error waiting for target flash write algorithm error writing to flash at address 0x08000000 at offset 0x00000000
The TRST/SRST error do not appear if I also eliminate the “connect_assert_srst” statement from
scripts/target/stm32l4x.cfg. The remainder is the sa
;){kind=link}