Posted by juriedutoit on 2016-07-05 09:13

Good day, I am new to the forum.
I have a custom PCB with a STM32F746IG. I have Crossworks and I can program the device via the FT2232D on my PCB, but I would like to move to a free development environment.

I have a FT2232D which I am using to program/debug the device. The TCLK, TDI, TDO and TMS signals are connected in CASE 1 in the stm32f7xx.cfg file I have set rest_config none and in the interface/ftdi/programmer.cfg I have set nSRST to -data 0x0000 -noe 0x0000 and I have a second PCB which is wired with TCLK, TDI, TDO and TMS AND SRST.as CASE 2using the default stm32f7xx.cfg file, the interface/ftdi/programmer.cfg I have set nSRST to -data 0x0010 -oe 0x0010.

In both cases I get errors when trying to program teh STM32f746. Please see below the 2 different error cases. I would prefer the system to be programmable as in case 1.

CASE1 error:
”
Open On-Chip Debugger 0.10.0-dev-00267-g884c33c (2016-03-16-12:22)
Licensed under GNU GPL v2
For bug reports, read
http://openocd.org/doc/doxygen/bugs.html
User : 13 6 command.c:546 command_print(): debug_level: 3
Debug: 14 6 command.c:145 script_debug(): command - ocd_command ocd_command type ocd_adapter_khz 500
Debug: 15 7 command.c:145 script_debug(): command - adapter_khz ocd_adapter_khz 500
Debug: 17 7 core.c:1633 jtag_config_khz(): handle jtag khz
Debug: 18 7 core.c:1600 adapter_khz_to_speed(): convert khz to interface specific speed value
Debug: 19 7 core.c:1600 adapter_khz_to_speed(): convert khz to interface specific speed value
User : 20 8 command.c:546 command_print(): adapter speed: 500 kHz
Debug: 21 8 configuration.c:84 find_file(): found C:\Ac6\SystemWorkbench\plugins\fr.ac6.mcu.debug_1.8.0.201603291114\resources\openocd\scripts\interface\ftdi\ft2232d.cfg
Debug: 22 9 command.c:145 script_debug(): command - ocd_command ocd_command type ocd_interface ftdi
Debug: 23 9 command.c:145 script_debug(): command - interface ocd_interface ftdi
Debug: 25 9 command.c:366 register_command_handler(): registering ‘ocd_ftdi_device_desc’...
Debug: 26 9 command.c:366 register_command_handler(): registering ‘ocd_ftdi_serial’...
Debug: 27 10 command.c:366 register_command_handler(): registering ‘ocd_ftdi_channel’...
Debug: 28 11 command.c:366 register_command_handler(): registering ‘ocd_ftdi_layout_init’...
Debug: 29 12 command.c:366 register_command_handler(): registering ‘ocd_ftdi_layout_signal’...
Debug: 30 12 command.c:366 register_command_handler(): registering ‘ocd_ftdi_set_signal’...
Debug: 31 12 command.c:366 register_command_handler(): registering ‘ocd_ftdi_vid_pid’...
Debug: 32 12 command.c:366 register_command_handler(): registering ‘ocd_ftdi_tdo_sample_edge’...
Debug: 33 13 command.c:145 script_debug(): command - ocd_command ocd_command type ocd_ftdi_vid_pid 0x0403 0x6010
Debug: 34 13 command.c:145 script_debug(): command - ftdi_vid_pid ocd_ftdi_vid_pid 0x0403 0x6010
Debug: 36 13 command.c:145 script_debug(): command - ocd_command ocd_command type ocd_ftdi_channel 0
Debug: 37 13 command.c:145 script_debug(): command - ftdi_channel ocd_ftdi_channel 0
Debug: 39 14 command.c:145 script_debug(): command - ocd_command ocd_command type ocd_ftdi_layout_init 0x0c28 0x0f0b
Debug: 40 14 command.c:145 script_debug(): command - ftdi_layout_init ocd_ftdi_layout_init 0x0c28 0x0f0b
Debug: 42 14 command.c:145 script_debug(): command - ocd_command ocd_command type ocd_ftdi_layout_signal nTRST -data 0x0000 -oe 0x0000
Debug: 43 15 command.c:145 script_debug(): command - ftdi_layout_signal ocd_ftdi_layout_signal nTRST -data 0x0000 -oe 0x0000
Debug: 45 15 command.c:145 script_debug(): command - ocd_command ocd_command type ocd_ftdi_layout_signal nSRST -data 0x0010 -oe 0x0010
Debug: 46 17 command.c:145 script_debug(): command - ftdi_layout_signal ocd_ftdi_layout_signal nSRST -data 0x0010 -oe 0x0010
Debug: 48 17 command.c:145 script_debug(): command - ocd_command ocd_command type ocd_transport select jtag
Debug: 49 18 command.c:145 script_debug(): command - ocd_transport ocd_transport select jtag
Debug: 50 18 command.c:366 register_command_handler(): registering ‘ocd_jtag_flush_queue_sleep’...
Debug: 51 18 command.c:366 register_command_handler(): registering ‘ocd_jtag_rclk’...
Debug: 52 18 command.c:366 register_command_handler(): registering ‘ocd_jtag_ntrst_delay’...
Debug: 53 19 command.c:366 register_command_handler(): registering ‘ocd_jtag_ntrst_assert_width’...
Debug: 54 19 command.c:366 register_command_handler(): registering ‘ocd_scan_chain’...
Debug: 55 19 command.c:366 register_command_handler(): registering ‘ocd_jtag_reset’...
Debug: 56 19 command.c:366 register_command_handler(): registering ‘ocd_runtest’...
Debug: 57 20 command.c:366 register_command_handler(): registering ‘ocd_irscan’...
Debug: 58 20 command.c:366 register_command_handler(): registering ‘ocd_verify_ircapture’...
Debug: 59 20 command.c:366 register_command_handler(): registering ‘ocd_verify_jtag’...
Debug: 60 20 command.c:366 register_command_handler(): registering ‘ocd_tms_sequence’...
Debug: 61 20 command.c:366 register_command_handler(): registering ‘ocd_wait_srst_deassert’...
Debug: 62 21 command.c:366 register_command_handler(): registering ‘ocd_jtag’...
Debug: 63 21 command.c:366 register_command_handler(): registering ‘ocd_jtag’...
Debug: 64 21 command.c:366 register_command_handler(): registering ‘ocd_jtag’...
Debug: 65 21 command.c:366 register_command_handler(): registering ‘ocd_jtag’...
Debug: 66 21 command.c:366 register_command_handler(): registering ‘ocd_jtag’...
Debug: 67 21 command.c:366 register_command_handler(): registering ‘ocd_jtag’...
Debug: 68 22 command.c:366 register_command_handler(): registering ‘ocd_jtag’...
Debug: 69 22 command.c:366 register_command_handler(): registering ‘ocd_jtag’...
Debug: 70 22 command.c:366 register_command_handler(): registering ‘ocd_jtag’...
Debug: 71 22 command.c:366 register_command_handler(): registering ‘ocd_jtag’...
Debug: 72 22 command.c:366 register_command_handler(): registering ‘ocd_jtag’...
Debug: 73 22 command.c:366 register_command_handler(): registering ‘ocd_jtag’...
Debug: 74 23 command.c:366 register_command_handler(): registering ‘ocd_jtag’...
Debug: 75 23 command.c:366 register_command_handler(): registering ‘ocd_svf’...
Debug: 76 23 command.c:366 register_command_handler(): registering ‘ocd_xsvf’...
Debug: 77 23 configuration.c:84 find_file(): found C:\Ac6\SystemWorkbench\plugins\fr.ac6.mcu.debug_1.8.0.201603291114\resources\openocd\scripts\target\stm32f7x.cfg
Debug: 78 24 configuration.c:84 find_file(): found C:\Ac6\SystemWorkbench\plugins\fr.ac6.mcu.debug_1.8.0.201603291114\resources\openocd\scripts/target/swj-dp.tcl
Debug: 79 24 command.c:145 script_debug(): command - ocd_command ocd_command type ocd_transport select
Debug: 80 25 command.c:145 script_debug(): command - ocd_transport ocd_transport select
Debug: 81 25 configuration.c:84 find_file(): found C:\Ac6\SystemWorkbench\plugins\fr.ac6.mcu.debug_1.8.0.201603291114\resources\openocd\scripts/mem_helper.tcl
Debug: 82 26 command.c:145 script_debug(): command - ocd_command ocd_command type ocd_add_usage_text mrw address
Debug: 83 26 command.c:145 script_debug(): command - add_usage_text ocd_add_usage_text mrw address
Debug: 85 26 command.c:1100 help_add_command(): added ‘mrw’ help text
Debug: 86 26 command.c:145 script_debug(): command - ocd_command ocd_command type ocd_add_help_text mrw Returns value of word in memory.
Debug: 87 26 command.c:145 script_debug(): command - add_help_text ocd_add_help_text mrw Returns value of word in memory.
Debug: 89 27 command.c:1113 help_add_command(): added ‘mrw’ help text
Debug: 90 27 command.c:145 script_debug(): command - ocd_command ocd_command type ocd_add_usage_text mmw address setbits clearbits
Debug: 91 27 command.c:145 script_debug(): command - add_usage_text ocd_add_usage_text mmw address setbits clearbits
Debug: 93 27 command.c:1100 help_add_command(): added ‘mmw’ help text
Debug: 94 28 command.c:145 script_debug(): command - ocd_command ocd_command type ocd_add_help_text mmw Modify word in memory. new_val = (old_val & ~clearbits) | setbits;
Debug: 95 28 command.c:145 script_debug(): command - add_help_text ocd_add_help_text mmw Modify word in memory. new_val = (old_val & ~clearbits) | setbits;
Debug: 97 28 command.c:1113 help_add_command(): added ‘mmw’ help text
Debug: 98 28 command.c:145 script_debug(): command - ocd_command ocd_command type ocd_transport select
Debug: 99 29 command.c:145 script_debug(): command - ocd_transport ocd_transport select
Debug: 100 29 command.c:145 script_debug(): command - ocd_command ocd_command type ocd_transport select
Debug: 101 29 command.c:145 script_debug(): command - ocd_transport ocd_transport select
Debug: 102 29 command.c:145 script_debug(): command - ocd_command ocd_command type ocd_transport select
Debug: 103 30 command.c:145 script_debug(): command - ocd_transport ocd_transport select
Debug: 104 30 command.c:145 script_debug(): command - ocd_command ocd_command type ocd_transport select
Debug: 105 30 command.c:145 script_debug(): command - ocd_transport ocd_transport select
Debug: 106 30 command.c:145 script_debug(): command - ocd_command ocd_command type ocd_jtag newtap stm32f7x cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id 0x5ba00477
Debug: 107 31 command.c:145 script_debug(): command - ocd_jtag ocd_jtag newtap stm32f7x cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id 0x5ba00477
Debug: 108 31 tcl.c:551 jim_newtap_cmd(): Creating New Tap, Chip: stm32f7x, Tap: cpu, Dotted: stm32f7x.cpu, 8 params
Debug: 109 31 tcl.c:575 jim_newtap_cmd(): Processing option: -irlen
Debug: 110 31 tcl.c:575 jim_newtap_cmd(): Processing option: -ircapture
Debug: 111 31 tcl.c:575 jim_newtap_cmd(): Processing option: -irmask
Debug: 112 32 tcl.c:575 jim_newtap_cmd(): Processing option: -expected-id
Debug: 113 32 core.c:1306 jtag_tap_init(): Created Tap: stm32f7x.cpu @ abs position 0, irlen 4, capture: 0x1 mask: 0xf
Debug: 114 32 command.c:145 script_debug(): command - ocd_command ocd_command type ocd_transport select
Debug: 115 32 command.c:145 script_debug(): command - ocd_transport ocd_transport select
Debug: 116 33 command.c:145 script_debug(): command - ocd_command ocd_command type ocd_transport select
Debug: 117 33 command.c:145 script_debug(): command - ocd_transport ocd_transport select
Debug: 118 33 command.c:145 script_debug(): command - ocd_command ocd_command type ocd_transport select
Debug: 119 33 command.c:145 script_debug(): command - ocd_transport ocd_transport select
Debug: 120 33 command.c:145 script_debug(): command - ocd_command ocd_command type ocd_transport select
Debug: 121 33 command.c:145 script_debug(): command - ocd_transport ocd_transport select
Debug: 122 34 command.c:145 script_debug(): command - ocd_command ocd_command type ocd_jtag newtap stm32f7x bs -irlen 5 -expected-id 0x06449041 -expected-id 0x06451041
Debug: 123 34 command.c:145 script_debug(): command - ocd_jtag ocd_jtag newtap stm32f7x bs -irlen 5 -expected-id 0x06449041 -expected-id 0x06451041
Debug: 124 34 tcl.c:551 jim_newtap_cmd(): Creating New Tap, Chip: stm32f7x, Tap: bs, Dotted: stm32f7x.bs, 6 params
Debug: 125 34 tcl.c:575 jim_newtap_cmd(): Processing option: -irlen
Debug: 126 35 tcl.c:575 jim_newtap_cmd(): Processing option: -expected-id
Debug: 127 35 tcl.c:575 jim_newtap_cmd(): Processing option: -expected-id
Debug: 128 35 core.c:1306 jtag_tap_init(): Created Tap: stm32f7x.bs @ abs position 1, irlen 5, capture: 0x1 mask: 0x3
Debug: 129 35 command.c:145 script_debug(): command - ocd_command ocd_command type ocd_target create stm32f7x.cpu cortex_m -endian little -chain-position stm32f7x.cpu
Debug: 130 35 command.c:145 script_debug(): command - ocd_target ocd_target create stm32f7x.cpu cortex_m -endian little -chain-position stm32f7x.cpu
Debug: 131 36 target.c:1883 target_free_all_working_areas_restore(): freeing all working areas
Debug: 132 36 command.c:366 register_command_handler(): registering ‘ocd_arm’...
Debug: 133 36 command.c:366 register_command_handler(): registering ‘ocd_arm’...
Debug: 134 36 command.c:366 register_command_handler(): registering ‘ocd_arm’...
Debug: 135 36 command.c:366 register_command_handler(): registering ‘ocd_arm’...
Debug: 136 37 command.c:366 register_command_handler(): registering ‘ocd_arm’...
Debug: 137 37 command.c:366 register_command_handler(): registering ‘ocd_arm’...
Debug: 138 37 command.c:366 register_command_handler(): registering ‘ocd_dap’...
Debug: 139 37 command.c:366 register_command_handler(): registering ‘ocd_dap’...
Debug: 140 37 command.c:366 register_command_handler(): registering ‘ocd_dap’...
Debug: 141 38 command.c:366 register_command_handler(): registering ‘ocd_dap’...
Debug: 142 38 command.c:366 register_command_handler(): registering ‘ocd_dap’...
Debug: 143 38 command.c:366 register_command_handler(): registering ‘ocd_dap’...
Debug: 144 38 command.c:366 register_command_handler(): registering ‘ocd_dap’...
Debug: 145 38 command.c:366 register_command_handler(): registering ‘ocd_tpiu’...
Debug: 146 38 command.c:366 register_command_handler(): registering ‘ocd_itm’...
Debug: 147 39 command.c:366 register_command_handler(): registering ‘ocd_itm’...
Debug: 148 39 command.c:366 register_command_handler(): registering ‘ocd_cortex_m’...
Debug: 149 39 command.c:366 register_command_handler(): registering ‘ocd_cortex_m’...
Debug: 150 39 command.c:366 register_command_handler(): registering ‘ocd_cortex_m’...
Debug: 151 39 command.c:366 register_command_handler(): registering ‘ocd_stm32f7x.cpu’...
Debug: 152 40 command.c:366 register_command_handler(): registering ‘ocd_stm32f7x.cpu’...
Debug: 153 40 command.c:366 register_command_handler(): registering ‘ocd_stm32f7x.cpu’...
Debug: 154 40 command.c:366 register_command_handler(): registering ‘ocd_stm32f7x.cpu’...
Debug: 155 40 command.c:366 register_command_handler(): registering ‘ocd_stm32f7x.cpu’...
Debug: 156 40 command.c:366 register_command_handler(): registering ‘ocd_stm32f7x.cpu’...
Debug: 157 41 command.c:366 register_command_handler(): registering ‘ocd_stm32f7x.cpu’...
Debug: 158 41 command.c:366 register_command_handler(): registering ‘ocd_stm32f7x.cpu’...
Debug: 159 41 command.c:366 register_command_handler(): registering ‘ocd_stm32f7x.cpu’...
Debug: 160 41 command.c:366 register_command_handler(): registering ‘ocd_stm32f7x.cpu’...
Debug: 161 41 command.c:366 register_command_handler(): registering ‘ocd_stm32f7x.cpu’...
Debug: 162 41 command.c:366 register_command_handler(): registering ‘ocd_stm32f7x.cpu’...
Debug: 163 42 command.c:366 register_command_handler(): registering ‘ocd_stm32f7x.cpu’...
Debug: 164 42 command.c:366 register_command_handler(): registering ‘ocd_stm32f7x.cpu’...
Debug: 165 42 command.c:366 register_command_handler(): registering ‘ocd_stm32f7x.cpu’...
Debug: 166 42 command.c:366 register_command_handler(): registering ‘ocd_stm32f7x.cpu’...
Debug: 167 42 command.c:366 register_command_handler(): registering ‘ocd_stm32f7x.cpu’...
Debug: 168 42 command.c:366 register_command_handler(): registering ‘ocd_stm32f7x.cpu’...
Debug: 169 42 command.c:366 register_command_handler(): registering ‘ocd_stm32f7x.cpu’...
Debug: 170 43 command.c:366 register_command_handler(): registering ‘ocd_stm32f7x.cpu’...
Debug: 171 43 command.c:366 register_command_handler(): registering ‘ocd_stm32f7x.cpu’...
Debug: 172 43 command.c:366 register_command_handler(): registering ‘ocd_stm32f7x.cpu’...
Debug: 173 43 command.c:366 register_command_handler(): registering ‘ocd_stm32f7x.cpu’...
Debug: 174 43 command.c:366 register_command_handler(): registering ‘ocd_stm32f7x.cpu’...
Debug: 175 43 command.c:366 register_command_handler(): registering ‘ocd_stm32f7x.cpu’...
Debug: 176 44 command.c:366 register_command_handler(): registering ‘ocd_stm32f7x.cpu’...
Debug: 177 44 command.c:366 register_command_handler(): registering ‘ocd_stm32f7x.cpu’...
Debug: 178 44 command.c:366 register_command_handler(): registering ‘ocd_stm32f7x.cpu’...
Debug: 179 44 command.c:366 register_command_handler(): registering ‘ocd_stm32f7x.cpu’...
Debug: 180 44 command.c:366 register_command_handler(): registering ‘ocd_stm32f7x.cpu’...
Debug: 181 44 command.c:366 register_command_handler(): registering ‘ocd_stm32f7x.cpu’...
Debug: 182 45 command.c:366 register_command_handler(): registering ‘ocd_stm32f7x.cpu’...
Debug: 183 45 command.c:366 register_command_handler(): registering ‘ocd_stm32f7x.cpu’...
Debug: 184 45 command.c:366 register_command_handler(): registering ‘ocd_stm32f7x.cpu’...
Debug: 185 45 command.c:366 register_command_handler(): registering ‘ocd_stm32f7x.cpu’...
Debug: 186 45 command.c:366 register_command_handler(): registering ‘ocd_stm32f7x.cpu’...
Debug: 187 45 command.c:366 register_command_handler(): registering ‘ocd_stm32f7x.cpu’...
Debug: 188 45 command.c:366 register_command_handler(): registering ‘ocd_stm32f7x.cpu’...
Debug: 189 46 command.c:366 register_command_handler(): registering ‘ocd_stm32f7x.cpu’...
Debug: 190 46 command.c:366 register_command_handler(): registering ‘ocd_stm32f7x.cpu’...
Debug: 191 46 command.c:366 register_command_handler(): registering ‘ocd_stm32f7x.cpu’...
Debug: 192 46 command.c:366 register_command_handler(): registering ‘ocd_stm32f7x.cpu’...
Debug: 193 46 command.c:366 register_command_handler(): registering ‘ocd_stm32f7x.cpu’...
Debug: 194 46 command.c:145 script_debug(): command - ocd_command ocd_command type ocd_stm32f7x.cpu configure -work-area-phys 0x20000000 -work-area-size 0x50000 -work-area-backup 0
Debug: 195 47 command.c:145 script_debug(): command - ocd_stm32f7x.cpu ocd_stm32f7x.cpu configure -work-area-phys 0x20000000 -work-area-size 0x50000 -work-area-backup 0
Debug: 196 47 target.c:1883 target_free_all_working_areas_restore(): freeing all working areas
Debug: 197 47 target.c:1883 target_free_all_working_areas_restore(): freeing all working areas
Debug: 198 47 target.c:1883 target_free_all_working_areas_restore(): freeing all working areas
Debug: 199 48 command.c:145 script_debug(): command - ocd_command ocd_command type ocd_flash bank stm32f7x.flash stm32f7x 0 0 0 0 stm32f7x.cpu
Debug: 200 48 command.c:145 script_debug(): command - ocd_flash ocd_flash bank stm32f7x.flash stm32f7x 0 0 0 0 stm32f7x.cpu
Debug: 202 48 command.c:366 register_command_handler(): registering ‘ocd_stm32f7x’...
Debug: 203 48 command.c:366 register_command_handler(): registering ‘ocd_stm32f7x’...
Debug: 204 49 command.c:366 register_command_handler(): registering ‘ocd_stm32f7x’...
Debug: 205 49 tcl.c:1031 handle_flash_bank_command(): ‘stm32f7x’ driver usage field missing
Debug: 206 49 command.c:145 script_debug(): command - ocd_command ocd_command type ocd_adapter_khz 500
Debug: 207 49 command.c:145 script_debug(): command - adapter_khz ocd_adapter_khz 500
Debug: 209 49 core.c:1633 jtag_config_khz(): handle jtag khz
Debug: 210 50 core.c:1600 adapter_khz_to_speed(): convert khz to interface specific speed value
Debug: 211 50 core.c:1600 adapter_khz_to_speed(): convert khz to interface specific speed value
User : 212 50 command.c:546 command_print(): adapter speed: 500 kHz
Debug: 213 50 command.c:145 script_debug(): command - ocd_command ocd_command type ocd_reset_config none
Debug: 214 50 command.c:145 script_debug(): command - reset_config ocd_reset_config none
User : 216 50 command.c:546 command_print(): none separate
Debug: 217 50 command.c:145 script_debug(): command - ocd_command ocd_command type ocd_adapter_nsrst_delay 100
Debug: 218 51 command.c:145 script_debug(): command - adapter_nsrst_delay ocd_adapter_nsrst_delay 100
User : 220 51 command.c:546 command_print(): adapter_nsrst_delay: 100
Debug: 221 51 command.c:145 script_debug(): command - ocd_command ocd_command type ocd_transport select
Debug: 222 51 command.c:145 script_debug(): command - ocd_transport ocd_transport select
Debug: 223 51 command.c:145 script_debug(): command - ocd_command ocd_command type ocd_jtag_ntrst_delay 100
Debug: 224 52 command.c:145 script_debug(): command - jtag_ntrst_delay ocd_jtag_ntrst_delay 100
User : 226 52 command.c:546 command_print(): jtag_ntrst_delay: 100
Debug: 227 52 command.c:145 script_debug(): command - ocd_command ocd_command type ocd_transport select
Debug: 228 52 command.c:145 script_debug(): command - ocd_transport ocd_transport select
Debug: 229 52 command.c:145 script_debug(): command - ocd_command ocd_command type ocd_cortex_m reset_config sysresetreq
Debug: 230 53 command.c:145 script_debug(): command - ocd_cortex_m ocd_cortex_m reset_config sysresetreq
User : 232 53 command.c:546 command_print(): cortex_m reset_config sysresetreq
Debug: 233 53 command.c:145 script_debug(): command - ocd_command ocd_command type ocd_stm32f7x.cpu configure -event examine-end
# Enable debug during low power modes (uses more power)
# DBGMCU_CR |= DBG_STANDBY | DBG_STOP | DBG_SLEEP
mmw 0xE0042004 0x00000007 0

# Stop watchdog counters during halt
# DBGMCU_APB1_FZ |= DBG_IWDG_STOP | DBG_WWDG_STOP
mmw 0xE0042008 0x00001800 0

Debug: 234 54 command.c:145 script_debug(): command - ocd_stm32f7x.cpu ocd_stm32f7x.cpu configure -event examine-end
# Enable debug during low power modes (uses more power)
# DBGMCU_CR |= DBG_STANDBY | DBG_STOP | DBG_SLEEP
mmw 0xE0042004 0x00000007 0

# Stop watchdog counters during halt
# DBGMCU_APB1_FZ |= DBG_IWDG_STOP | DBG_WWDG_STOP
mmw 0xE0042008 0x00001800 0

Debug: 235 54 command.c:145 script_debug(): command - ocd_command ocd_command type ocd_stm32f7x.cpu configure -event gdb-attach
# Needed to be able to use the connect_assert_srst in reset_config
# otherwise, can’t read device flash size register
reset init

Debug: 236 55 command.c:145 script_debug(): command - ocd_stm32f7x.cpu ocd_stm32f7x.cpu configure -event gdb-attach
# Needed to be able to use the connect_assert_srst in reset_config
# otherwise, can’t read device flash size register
reset init

Debug: 237 55 command.c:145 script_debug(): command - ocd_command ocd_command type ocd_stm32f7x.cpu configure -event trace-config
# Set TRACE_IOEN; TRACE_MODE is set to async; when using sync
# change this value accordingly to configure trace pins
# assignment
mmw 0xE0042004 0x00000020 0

Debug: 238 56 command.c:145 script_debug(): command - ocd_stm32f7x.cpu ocd_stm32f7x.cpu configure -event trace-config
# Set TRACE_IOEN; TRACE_MODE is set to async; when using sync
# change this value accordingly to configure trace pins
# assignment
mmw 0xE0042004 0x00000020 0

Debug: 239 56 command.c:145 script_debug(): command - ocd_command ocd_command type ocd_stm32f7x.cpu configure -event reset-init
# Configure PLL to boost clock to HSI x 4 (64 MHz)
mww 0x40023804 0x08012008 ;# RCC_PLLCFGR 16 Mhz /8 (M) * 128 (N) /4(P)
mww 0x40023C00 0x00000102 ;# FLASH_ACR = PRFTBE | 2(Latency)
mmw 0x40023800 0x01000000 0 ;# RCC_CR |= PLLON
sleep 10 ;# Wait for PLL to lock
mmw 0x40023808 0x00001000 0 ;# RCC_CFGR |= RCC_CFGR_PPRE1_DIV2
mmw 0x40023808 0x00000002 0 ;# RCC_CFGR |= RCC_CFGR_SW_PLL

# Boost JTAG frequency

1. adapter_khz 8000

adapter_khz 500

Debug: 240 57 command.c:145 script_debug(): command - ocd_stm32f7x.cpu ocd_stm32f7x.cpu configure -event reset-init
# Configure PLL to boost clock to HSI x 4 (64 MHz)
mww 0x40023804 0x08012008 ;# RCC_PLLCFGR 16 Mhz /8 (M) * 128 (N) /4(P)
mww 0x40023C00 0x00000102 ;# FLASH_ACR = PRFTBE | 2(Latency)
mmw 0x40023800 0x01000000 0 ;# RCC_CR |= PLLON
sleep 10 ;# Wait for PLL to lock
mmw 0x40023808 0x00001000 0 ;# RCC_CFGR |= RCC_CFGR_PPRE1_DIV2
mmw 0x40023808 0x00000002 0 ;# RCC_CFGR |= RCC_CFGR_SW_PLL

# Boost JTAG frequency

1. adapter_khz 8000

adapter_khz 500

Debug: 241 58 command.c:145 script_debug(): command - ocd_command ocd_command type ocd_scan_chain
Debug: 242 58 command.c:145 script_debug(): command - scan_chain ocd_scan_chain
User : 244 58 command.c:546 command_print(): TapName Enabled IdCode Expected IrLen IrCap IrMask
User : 245 58 command.c:546 command_print(): — ------- ---- ---- ---- --- - ----
User : 246 59 command.c:546 command_print(): 0 stm32f7x.cpu Y 0x00000000 0x5ba00477 4 0x01 0x0f
User : 247 59 command.c:546 command_print(): 1 stm32f7x.bs Y 0x00000000 0x06449041 5 0x01 0x03
User : 248 59 command.c:546 command_print(): 0x06451041
Debug: 249 59 command.c:145 script_debug(): command - ocd_command ocd_command type ocd_init
Debug: 250 59 command.c:145 script_debug(): command - init ocd_init
Debug: 252 60 command.c:145 script_debug(): command - ocd_command ocd_command type ocd_target init
Debug: 253 60 command.c:145 script_debug(): command - ocd_target ocd_target init
Debug: 255 60 command.c:145 script_debug(): command - ocd_command ocd_command type ocd_target names
Debug: 256 60 command.c:145 script_debug(): command - ocd_target ocd_target names
Debug: 257 60 command.c:145 script_debug(): command - ocd_command ocd_command type ocd_stm32f7x.cpu cget -event gdb-flash-erase-start
Debug: 258 61 command.c:145 script_debug(): command - ocd_stm32f7x.cpu ocd_stm32f7x.cpu cget -event gdb-flash-erase-start
Debug: 259 61 command.c:145 script_debug(): command - ocd_command ocd_command type ocd_stm32f7x.cpu configure -event gdb-flash-erase-start reset init
Debug: 260 61 command.c:145 script_debug(): command - ocd_stm32f7x.cpu ocd_stm32f7x.cpu configure -event gdb-flash-erase-start reset init
Debug: 261 61 command.c:145 script_debug(): command - ocd_command ocd_command type ocd_stm32f7x.cpu cget -event gdb-flash-write-end
Debug: 262 62 command.c:145 script_debug(): command - ocd_stm32f7x.cpu ocd_stm32f7x.cpu cget -event gdb-flash-write-end
Debug: 263 62 command.c:145 script_debug(): command - ocd_command ocd_command type ocd_stm32f7x.cpu configure -event gdb-flash-write-end reset halt
Debug: 264 62 command.c:145 script_debug(): command - ocd_stm32f7x.cpu ocd_stm32f7x.cpu configure -event gdb-flash-write-end reset halt
Debug: 265 62 target.c:1308 handle_target_init_command(): Initializing targets...
Debug: 266 63 command.c:366 register_command_handler(): registering ‘ocd_target_request’...
Debug: 267 63 command.c:366 register_command_handler(): registering ‘ocd_trace’...
Debug: 268 63 command.c:366 register_command_handler(): registering ‘ocd_trace’...
Debug: 269 63 command.c:366 register_command_handler(): registering ‘ocd_fast_load_image’...
Debug: 270 63 command.c:366 register_command_handler(): registering ‘ocd_fast_load’...
Debug: 271 63 command.c:366 register_command_handler(): registering ‘ocd_profile’...
Debug: 272 64 command.c:366 register_command_handler(): registering ‘ocd_virt2phys’...
Debug: 273 64 command.c:366 register_command_handler(): registering ‘ocd_reg’...
Debug: 274 64 command.c:366 register_command_handler(): registering ‘ocd_poll’...
Debug: 275 64 command.c:366 register_command_handler(): registering ‘ocd_wait_halt’...
Debug: 276 64 command.c:366 register_command_handler(): registering ‘ocd_halt’...
Debug: 277 64 command.c:366 register_command_handler(): registering ‘ocd_resume’...
Debug: 278 64 command.c:366 register_command_handler(): registering ‘ocd_reset’...
Debug: 279 65 command.c:366 register_command_handler(): registering ‘ocd_soft_reset_halt’...
Debug: 280 65 command.c:366 register_command_handler(): registering ‘ocd_step’...
Debug: 281 65 command.c:366 register_command_handler(): registering ‘ocd_mdw’...
Debug: 282 65 command.c:366 register_command_handler(): registering ‘ocd_mdh’...
Debug: 283 65 command.c:366 register_command_handler(): registering ‘ocd_mdb’...
Debug: 284 65 command.c:366 register_command_handler(): registering ‘ocd_mww’...
Debug: 285 66 command.c:366 register_command_handler(): registering ‘ocd_mwh’...
Debug: 286 66 command.c:366 register_command_handler(): registering ‘ocd_mwb’...
Debug: 287 66 command.c:366 register_command_handler(): registering ‘ocd_bp’...
Debug: 288 66 command.c:366 register_command_handler(): registering ‘ocd_rbp’...
Debug: 289 66 command.c:366 register_command_handler(): registering ‘ocd_wp’...
Debug: 290 66 command.c:366 register_command_handler(): registering ‘ocd_rwp’...
Debug: 291 66 command.c:366 register_command_handler(): registering ‘ocd_load_image’...
Debug: 292 67 command.c:366 register_command_handler(): registering ‘ocd_dump_image’...
Debug: 293 67 command.c:366 register_command_handler(): registering ‘ocd_verify_image’...
Debug: 294 67 command.c:366 register_command_handler(): registering ‘ocd_test_image’...
Debug: 295 67 command.c:366 register_command_handler(): registering ‘ocd_reset_nag’...
Debug: 296 67 command.c:366 register_command_handler(): registering ‘ocd_ps’...
Debug: 297 68 command.c:366 register_command_handler(): registering ‘ocd_test_mem_access’...
Debug: 298 68 ftdi.c:630 ftdi_initialize(): ftdi interface using shortest path jtag state transitions
Error: 299 147 mpsse.c:140 open_matching_device(): libusb_open() failed with LIBUSB_ERROR_NOT_SUPPORTED
Debug: 300 148 mpsse.c:363 mpsse_purge(): -
Debug: 301 149 mpsse.c:644 mpsse_loopback_config(): off
Debug: 302 149 mpsse.c:689 mpsse_set_frequency(): target 500000 Hz
Debug: 303 149 mpsse.c:650 mpsse_set_divisor(): 11
Debug: 304 149 mpsse.c:713 mpsse_set_frequency(): actually 500000 Hz
Debug: 305 149 core.c:1600 adapter_khz_to_speed(): convert khz to interface specific speed value
Debug: 306 150 core.c:1603 adapter_khz_to_speed(): have interface set up
Debug: 307 150 mpsse.c:689 mpsse_set_frequency(): target 500000 Hz
Debug: 308 150 mpsse.c:650 mpsse_set_divisor(): 11
Debug: 309 150 mpsse.c:713 mpsse_set_frequency(): actually 500000 Hz
Debug: 310 150 core.c:1600 adapter_khz_to_speed(): convert khz to interface specific speed value
Debug: 311 150 core.c:1603 adapter_khz_to_speed(): have interface set up
Info : 312 150 core.c:1388 adapter_init(): clock speed 500 kHz
Debug: 313 151 openocd.c:137 handle_init_command(): Debug Adapter init complete
Debug: 314 151 command.c:145 script_debug(): command - ocd_command ocd_command type ocd_transport init
Debug: 315 151 command.c:145 script_debug(): command - ocd_transport ocd_transport init
Debug: 317 151 transport.c:240 handle_transport_init(): handle_transport_init
Debug: 318 152 core.c:731 jtag_add_reset(): SRST line released
Debug: 319 152 core.c:755 jtag_add_reset(): TRST line released
Debug: 320 152 core.c:329 jtag_call_event_callbacks(): jtag event: TAP reset
Debug: 321 369 command.c:145 script_debug(): command - ocd_command ocd_command type ocd_jtag arp_init
Debug: 322 369 command.c:145 script_debug(): command - ocd_jtag ocd_jtag arp_init
Debug: 323 369 core.c:1401 jtag_init_inner(): Init JTAG chain
Debug: 324 369 core.c:329 jtag_call_event_callbacks(): jtag event: TAP reset
Debug: 325 369 core.c:1062 jtag_examine_chain(): DR scan interrogation for IDCODE/BYPASS
Debug: 326 370 core.c:329 jtag_call_event_callbacks(): jtag event: TAP reset
Info : 327 372 core.c:961 jtag_examine_chain_display(): JTAG tap: stm32f7x.cpu tap/device found: 0x5ba00477 (mfg: 0x23b (ARM Ltd.), part: 0xba00, ver: 0x5)
Info : 328 372 core.c:961 jtag_examine_chain_display(): JTAG tap: stm32f7x.bs tap/device found: 0x06449041 (mfg: 0x020 (STMicroelectronics), part: 0x6449, ver: 0x0)
Debug: 329 372 core.c:1192 jtag_validate_ircapture(): IR capture validation scan
Debug: 330 373 core.c:1250 jtag_validate_ircapture(): stm32f7x.cpu: IR capture 0x01
Debug: 331 373 core.c:1250 jtag_validate_ircapture(): stm32f7x.bs: IR capture 0x01
Debug: 332 373 openocd.c:150 handle_init_command(): Examining targets...
Debug: 333 373 target.c:1501 target_call_event_callbacks(): target event 21 (examine-start)
Debug: 334 373 arm_adi_v5.c:605 dap_dp_init():
Debug: 335 373 arm_adi_v5.c:638 dap_dp_init(): DAP: wait CDBGPWRUPACK
Debug: 336 373 arm_adi_v5.h:427 dap_dp_poll_register(): DAP: poll 4, mask 0x20000000, value 0x20000000
Debug: 337 375 arm_adi_v5.c:645 dap_dp_init(): DAP: wait CSYSPWRUPACK
Debug: 338 375 arm_adi_v5.h:427 dap_dp_poll_register(): DAP: poll 4, mask 0x80000000, value 0x80000000
Debug: 339 378 arm_adi_v5.c:789 dap_find_ap(): Found AHB-AP at AP index: 0 (IDR=0x74770001)
Debug: 340 380 arm_adi_v5.c:716 mem_ap_init(): MEM_AP Packed Transfers: enabled
Debug: 341 380 arm_adi_v5.c:727 mem_ap_init(): MEM_AP CFG: large data 0, long address 0, big-endian 0
Debug: 342 381 target.c:2226 target_read_u32(): address: 0xe000ed00, value: 0x410fc271
Debug: 343 382 cortex_m.c:1930 cortex_m_examine(): Cortex-M7 r0p1 processor detected
Debug: 344 382 cortex_m.c:1931 cortex_m_examine(): cpuid: 0x410fc271
Debug: 345 382 target.c:2314 target_write_u32(): address: 0xe000edfc, value: 0x01000000
Debug: 346 384 target.c:2226 target_read_u32(): address: 0xe0002000, value: 0x10000081
Debug: 347 384 target.c:2314 target_write_u32(): address: 0xe0002008, value: 0x00000000
Debug: 348 385 target.c:2314 target_write_u32(): address: 0xe000200c, value: 0x00000000
Debug: 349 387 target.c:2314 target_write_u32(): address: 0xe0002010, value: 0x00000000
Debug: 350 388 target.c:2314 target_write_u32(): address: 0xe0002014, value: 0x00000000
Debug: 351 389 target.c:2314 target_write_u32(): address: 0xe0002018, value: 0x00000000
Debug: 352 390 target.c:2314 target_write_u32(): address: 0xe000201c, value: 0x00000000
Debug: 353 392 target.c:2314 target_write_u32(): address: 0xe0002020, value: 0x00000000
Debug: 354 393 target.c:2314 target_write_u32(): address: 0xe0002024, value: 0x00000000
Debug: 355 394 cortex_m.c:2005 cortex_m_examine(): FPB fpcr 0x10000081, numcode 8, numlit 0
Debug: 356 396 target.c:2226 target_read_u32(): address: 0xe0001000, value: 0x40000000
Debug: 357 396 target.c:2314 target_write_u32(): address: 0xe0001028, value: 0x00000000
Debug: 358 397 target.c:2314 target_write_u32(): address: 0xe0001038, value: 0x00000000
Debug: 359 398 target.c:2314 target_write_u32(): address: 0xe0001048, value: 0x00000000
Debug: 360 399 target.c:2314 target_write_u32(): address: 0xe0001058, value: 0x00000000
Debug: 361 400 cortex_m.c:1849 cortex_m_dwt_setup(): DWT dwtcr 0x40000000, comp 4, watch/trigger
Info : 362 401 cortex_m.c:2015 cortex_m_examine(): stm32f7x.cpu: hardware has 8 breakpoints, 4 watchpoints
Debug: 363 401 target.c:1501 target_call_event_callbacks(): target event 22 (examine-end)
Debug: 364 401 target.c:4256 target_handle_event(): target: (0) stm32f7x.cpu (cortex_m) event: 22 (examine-end) action:
# Enable debug during low power modes (uses more power)
# DBGMCU_CR |= DBG_STANDBY | DBG_STOP | DBG_SLEEP
mmw 0xE0042004 0x00000007 0

# Stop watchdog counters during halt
# DBGMCU_APB1_FZ |= DBG_IWDG_STOP | DBG_WWDG_STOP
mmw 0xE0042008 0x00001800 0

Debug: 365 403 command.c:145 script_debug(): command - ocd_command ocd_command type ocd_mww 0xE0042004 7
Debug: 366 404 command.c:145 script_debug(): command - mww ocd_mww 0xE0042004 7
Debug: 368 408 command.c:145 script_debug(): command - ocd_command ocd_command type ocd_mww 0xE0042008 6144
Debug: 369 408 command.c:145 script_debug(): command - mww ocd_mww 0xE0042008 6144
Debug: 371 411 command.c:145 script_debug(): command - ocd_command ocd_command type ocd_flash init
Debug: 372 411 command.c:145 script_debug(): command - ocd_flash ocd_flash init
Debug: 374 413 tcl.c:1097 handle_flash_init_command(): Initializing flash devices...
Debug: 375 413 command.c:366 register_command_handler(): registering ‘ocd_flash’...
Debug: 376 413 command.c:366 register_command_handler(): registering ‘ocd_flash’...
Debug: 377 413 command.c:366 register_command_handler(): registering ‘ocd_flash’...
Debug: 378 414 command.c:366 register_command_handler(): registering ‘ocd_flash’...
Debug: 379 414 command.c:366 register_command_handler(): registering ‘ocd_flash’...
Debug: 380 414 command.c:366 register_command_handler(): registering ‘ocd_flash’...
Debug: 381 414 command.c:366 register_command_handler(): registering ‘ocd_flash’...
Debug: 382 414 command.c:366 register_command_handler(): registering ‘ocd_flash’...
Debug: 383 415 command.c:366 register_command_handler(): registering ‘ocd_flash’...
Debug: 384 415 command.c:366 register_command_handler(): registering ‘ocd_flash’...
Debug: 385 415 command.c:366 register_command_handler(): registering ‘ocd_flash’...
Debug: 386 415 command.c:366 register_command_handler(): registering ‘ocd_flash’...
Debug: 387 415 command.c:366 register_command_handler(): registering ‘ocd_flash’...
Debug: 388 415 command.c:366 register_command_handler(): registering ‘ocd_flash’...
Debug: 389 416 command.c:366 register_command_handler(): registering ‘ocd_flash’...
Debug: 390 416 command.c:145 script_debug(): command - ocd_command ocd_command type ocd_mflash init
Debug: 391 416 command.c:145 script_debug(): command - ocd_mflash ocd_mflash init
Debug: 393 417 mflash.c:1379 handle_mflash_init_command(): Initializing mflash devices...
Debug: 394 419 command.c:145 script_debug(): command - ocd_command ocd_command type ocd_nand init
Debug: 395 419 command.c:145 script_debug(): command - ocd_nand ocd_nand init
Debug: 397 420 tcl.c:497 handle_nand_init_command(): Initializing NAND devices...
Debug: 398 420 command.c:145 script_debug(): command - ocd_command ocd_command type ocd_pld init
Debug: 399 421 command.c:145 script_debug(): command - ocd_pld ocd_pld init
Debug: 401 422 pld.c:207 handle_pld_init_command(): Initializing PLDs...
Debug: 402 424 command.c:145 script_debug(): command - ocd_command ocd_command type ocd_reset init
Debug: 403 424 command.c:145 script_debug(): command - reset ocd_reset init
Debug: 405 425 target.c:1519 target_call_reset_callbacks(): target reset 3 (init)
Debug: 406 425 command.c:145 script_debug(): command - ocd_command ocd_command type ocd_target names
Debug: 407 426 command.c:145 script_debug(): command - ocd_target ocd_target names
Debug: 408 426 command.c:145 script_debug(): command - ocd_command ocd_command type ocd_stm32f7x.cpu invoke-event reset-start
Debug: 409 426 command.c:145 script_debug(): command - ocd_stm32f7x.cpu ocd_stm32f7x.cpu invoke-event reset-start
Debug: 410 426 command.c:145 script_debug(): command - ocd_command ocd_command type ocd_transport select
Debug: 411 427 command.c:145 script_debug(): command - ocd_transport ocd_transport select
Debug: 412 427 command.c:145 script_debug(): command - ocd_command ocd_command type ocd_jtag arp_init-reset
Debug: 413 427 command.c:145 script_debug(): command - ocd_jtag ocd_jtag arp_init-reset
Debug: 414 427 core.c:1509 jtag_init_reset(): Initializing with hard TRST+SRST reset
Debug: 415 427 core.c:744 jtag_add_reset(): JTAG reset with TLR instead of TRST
Debug: 416 428 core.c:329 jtag_call_event_callbacks(): jtag event: TAP reset
Debug: 417 428 core.c:1401 jtag_init_inner(): Init JTAG chain
Debug: 418 428 core.c:329 jtag_call_event_callbacks(): jtag event: TAP reset
Debug: 419 428 core.c:1062 jtag_examine_chain(): DR scan interrogation for IDCODE/BYPASS
Debug: 420 429 core.c:329 jtag_call_event_callbacks(): jtag event: TAP reset
Info : 421 431 core.c:961 jtag_examine_chain_display(): JTAG tap: stm32f7x.cpu tap/device found: 0x5ba00477 (mfg: 0x23b (ARM Ltd.), part: 0xba00, ver: 0x5)
Info : 422 431 core.c:961 jtag_examine_chain_display(): JTAG tap: stm32f7x.bs tap/device found: 0x06449041 (mfg: 0x020 (STMicroelectronics), part: 0x6449, ver: 0x0)
Debug: 423 431 core.c:1192 jtag_validate_ircapture(): IR capture validation scan
Debug: 424 431 core.c:1250 jtag_validate_ircapture(): stm32f7x.cpu: IR capture 0x01
Debug: 425 432 core.c:1250 jtag_validate_ircapture(): stm32f7x.bs: IR capture 0x01
Debug: 426 432 command.c:145 script_debug(): command - ocd_command ocd_command type ocd_transport select
Debug: 427 432 command.c:145 script_debug(): command - ocd_transport ocd_transport select
Debug: 428 432 command.c:145 script_debug(): command - ocd_command ocd_command type ocd_stm32f7x.cpu cget -chain-position
Debug: 429 432 command.c:145 script_debug(): command - ocd_stm32f7x.cpu ocd_stm32f7x.cpu cget -chain-position
Debug: 430 433 command.c:145 script_debug(): command - ocd_command ocd_command type ocd_jtag tapisenabled stm32f7x.cpu
Debug: 431 433 command.c:145 script_debug(): command - ocd_jtag ocd_jtag tapisenabled stm32f7x.cpu
Debug: 432 433 command.c:145 script_debug(): command - ocd_command ocd_command type ocd_stm32f7x.cpu invoke-event examine-start
Debug: 433 433 command.c:145 script_debug(): command - ocd_stm32f7x.cpu ocd_stm32f7x.cpu invoke-event examine-start
Debug: 434 434 command.c:145 script_debug(): command - ocd_command ocd_command type ocd_stm32f7x.cpu arp_examine
Debug: 435 435 command.c:145 script_debug(): command - ocd_stm32f7x.cpu ocd_stm32f7x.cpu arp_examine
Debug: 436 435 arm_adi_v5.c:605 dap_dp_init():
Debug: 437 435 arm_adi_v5.c:638 dap_dp_init(): DAP: wait CDBGPWRUPACK
Debug: 438 435 arm_adi_v5.h:427 dap_dp_poll_register(): DAP: poll 4, mask 0x20000000, value 0x20000000
Debug: 439 437 arm_adi_v5.c:645 dap_dp_init(): DAP: wait CSYSPWRUPACK
Debug: 440 437 arm_adi_v5.h:427 dap_dp_poll_register(): DAP: poll 4, mask 0x80000000, value 0x80000000
Debug: 441 441 arm_adi_v5.c:789 dap_find_ap(): Found AHB-AP at AP index: 0 (IDR=0x74770001)
Debug: 442 443 arm_adi_v5.c:716 mem_ap_init(): MEM_AP Packed Transfers: enabled
Debug: 443 443 arm_adi_v5.c:727 mem_ap_init(): MEM_AP CFG: large data 0, long address 0, big-endian 0
Debug: 444 443 command.c:145 script_debug(): command - ocd_command ocd_command type ocd_stm32f7x.cpu invoke-event examine-end
Debug: 445 443 command.c:145 script_debug(): command - ocd_stm32f7x.cpu ocd_stm32f7x.cpu invoke-event examine-end
Debug: 446 444 target.c:4256 target_handle_event(): target: (0) stm32f7x.cpu (cortex_m) event: 22 (examine-end) action:
# Enable debug during low power modes (uses more power)
# DBGMCU_CR |= DBG_STANDBY | DBG_STOP | DBG_SLEEP
mmw 0xE0042004 0x00000007 0

# Stop watchdog counters during halt
# DBGMCU_APB1_FZ |= DBG_IWDG_STOP | DBG_WWDG_STOP
mmw 0xE0042008 0x00001800 0

Debug: 447 446 command.c:145 script_debug(): command - ocd_command ocd_command type ocd_mww 0xE0042004 7
Debug: 448 446 command.c:145 script_debug(): command - mww ocd_mww 0xE0042004 7
Debug: 450 449 command.c:145 script_debug(): command - ocd_command ocd_command type ocd_mww 0xE0042008 6144
Debug: 451 449 command.c:145 script_debug(): command - mww ocd_mww 0xE0042008 6144
Debug: 453 450 command.c:145 script_debug(): command - ocd_command ocd_command type ocd_stm32f7x.cpu invoke-event reset-assert-pre
Debug: 454 451 command.c:145 script_debug(): command - ocd_stm32f7x.cpu ocd_stm32f7x.cpu invoke-event reset-assert-pre
Debug: 455 451 command.c:145 script_debug(): command - ocd_command ocd_command type ocd_transport select
Debug: 456 451 command.c:145 script_debug(): command - ocd_transport ocd_transport select
Debug: 457 451 command.c:145 script_debug(): command - ocd_command ocd_command type ocd_stm32f7x.cpu cget -chain-position
Debug: 458 452 command.c:145 script_debug(): command - ocd_stm32f7x.cpu ocd_stm32f7x.cpu cget -chain-position
Debug: 459 452 command.c:145 script_debug(): command - ocd_command ocd_command type ocd_jtag tapisenabled stm32f7x.cpu
Debug: 460 452 command.c:145 script_debug(): command - ocd_jtag ocd_jtag tapisenabled stm32f7x.cpu
Debug: 461 452 command.c:145 script_debug(): command - ocd_command ocd_command type ocd_stm32f7x.cpu arp_reset assert 1
Debug: 462 453 command.c:145 script_debug(): command - ocd_stm32f7x.cpu ocd_stm32f7x.cpu arp_reset assert 1
Debug: 463 453 target.c:1883 target_free_all_working_areas_restore(): freeing all working areas
Debug: 464 453 cortex_m.c:967 cortex_m_assert_reset(): target->state: running
Debug: 465 456 cortex_m.c:1053 cortex_m_assert_reset(): Using Cortex-M SYSRESETREQ
Debug: 466 457 arm_adi_v5.c:605 dap_dp_init():
Debug: 467 457 arm_adi_v5.c:638 dap_dp_init(): DAP: wait CDBGPWRUPACK
Debug: 468 457 arm_adi_v5.h:427 dap_dp_poll_register(): DAP: poll 4, mask 0x20000000, value 0x20000000
Debug: 469 459 arm_adi_v5.c:645 dap_dp_init(): DAP: wait CSYSPWRUPACK
Debug: 470 459 arm_adi_v5.h:427 dap_dp_poll_register(): DAP: poll 4, mask 0x80000000, value 0x80000000
Debug: 471 462 cortex_m.c:585 cortex_m_halt(): target->state: reset
Debug: 472 462 command.c:145 script_debug(): command - ocd_command ocd_command type ocd_stm32f7x.cpu invoke-event reset-assert-post
Debug: 473 463 command.c:145 script_debug(): command - ocd_stm32f7x.cpu ocd_stm32f7x.cpu invoke-event reset-assert-post
Debug: 474 463 command.c:145 script_debug(): command - ocd_command ocd_command type ocd_stm32f7x.cpu invoke-event reset-deassert-pre
Debug: 475 463 command.c:145 script_debug(): command - ocd_stm32f7x.cpu ocd_stm32f7x.cpu invoke-event reset-deassert-pre
Debug: 476 464 command.c:145 script_debug(): command - ocd_command ocd_command type ocd_transport select
Debug: 477 464 command.c:145 script_debug(): command - ocd_transport ocd_transport select
Debug: 478 464 command.c:145 script_debug(): command - ocd_command ocd_command type ocd_stm32f7x.cpu cget -chain-position
Debug: 479 464 command.c:145 script_debug(): command - ocd_stm32f7x.cpu ocd_stm32f7x.cpu cget -chain-position
Debug: 480 465 command.c:145 script_debug(): command - ocd_command ocd_command type ocd_jtag tapisenabled stm32f7x.cpu
Debug: 481 465 command.c:145 script_debug(): command - ocd_jtag ocd_jtag tapisenabled stm32f7x.cpu
Debug: 482 465 command.c:145 script_debug(): command - ocd_command ocd_command type ocd_stm32f7x.cpu arp_reset deassert 1
Debug: 483 465 command.c:145 script_debug(): command - ocd_stm32f7x.cpu ocd_stm32f7x.cpu arp_reset deassert 1
Debug: 484 465 target.c:1883 target_free_all_working_areas_restore(): freeing all working areas
Debug: 485 466 cortex_m.c:1103 cortex_m_deassert_reset(): target->state: reset
Debug: 486 466 command.c:145 script_debug(): command - ocd_command ocd_command type ocd_stm32f7x.cpu invoke-event reset-deassert-post
Debug: 487 466 command.c:145 script_debug(): command - ocd_stm32f7x.cpu ocd_stm32f7x.cpu invoke-event reset-deassert-post
Debug: 488 466 command.c:145 script_debug(): command - ocd_command ocd_command type ocd_transport select
Debug: 489 467 command.c:145 script_debug(): command - ocd_transport ocd_transport select
Debug: 490 467 command.c:145 script_debug(): command - ocd_command ocd_command type ocd_stm32f7x.cpu cget -chain-position
Debug: 491 467 command.c:145 script_debug(): command - ocd_stm32f7x.cpu ocd_stm32f7x.cpu cget -chain-position
Debug: 492 467 command.c:145 script_debug(): command - ocd_command ocd_command type ocd_jtag tapisenabled stm32f7x.cpu
Debug: 493 468 command.c:145 script_debug(): command - ocd_jtag ocd_jtag tapisenabled stm32f7x.cpu
Debug: 494 468 command.c:145 script_debug(): command - ocd_command ocd_command type ocd_stm32f7x.cpu arp_waitstate halted 1000
Debug: 495 468 command.c:145 script_debug(): command - ocd_stm32f7x.cpu ocd_stm32f7x.cpu arp_waitstate halted 1000
Debug: 497 524 target.c:2788 target_wait_state(): waiting for target halted...
Debug: 498 525 cortex_m.c:531 cortex_m_poll(): Exit from reset with dcb_dhcsr 0x30003
Debug: 499 527 cortex_m.c:235 cortex_m_endreset_event(): DCB_DEMCR = 0x01000501
Debug: 500 529 target.c:2314 target_write_u32(): address: 0xe0002000, value: 0x00000003
Debug: 501 531 target.c:2226 target_read_u32(): address: 0xe0002000, value: 0x10000081
Debug: 502 532 target.c:2314 target_write_u32(): address: 0xe0002008, value: 0x00000000
Debug: 503 533 target.c:2314 target_write_u32(): address: 0xe000200c, value: 0x00000000
Debug: 504 534 target.c:2314 target_write_u32(): address: 0xe0002010, value: 0x00000000
Debug: 505 535 target.c:2314 target_write_u32(): address: 0xe0002014, value: 0x00000000
Debug: 506 536 target.c:2314 target_write_u32(): address: 0xe0002018, value: 0x00000000
Debug: 507 538 target.c:2314 target_write_u32(): address: 0xe000201c, value: 0x00000000
Debug: 508 539 target.c:2314 target_write_u32(): address: 0xe0002020, value: 0x00000000
Debug: 509 540 target.c:2314 target_write_u32(): address: 0xe0002024, value: 0x00000000
Debug: 510 542 target.c:2314 target_write_u32(): address: 0xe0001020, value: 0x00000000
Debug: 511 543 target.c:2314 target_write_u32(): address: 0xe0001024, value: 0x00000000
Debug: 512 544 target.c:2314 target_write_u32(): address: 0xe0001028, value: 0x00000000
Debug: 513 545 target.c:2314 target_write_u32(): address: 0xe0001030, value: 0x00000000
Debug: 514 547 target.c:2314 target_write_u32(): address: 0xe0001034, value: 0x00000000
Debug: 515 548 target.c:2314 target_write_u32(): address: 0xe0001038, value: 0x00000000
Debug: 516 549 target.c:2314 target_write_u32(): address: 0xe0001040, value: 0x00000000
Debug: 517 550 target.c:2314 target_write_u32(): address: 0xe0001044, value: 0x00000000
Debug: 518 551 target.c:2314 target_write_u32(): address: 0xe0001048, value: 0x00000000
Debug: 519 553 target.c:2314 target_write_u32(): address: 0xe0001050, value: 0x00000000
Debug: 520 554 target.c:2314 target_write_u32(): address: 0xe0001054, value: 0x00000000
Debug: 521 555 target.c:2314 target_write_u32(): address: 0xe0001058, value: 0x00000000
Debug: 522 558 cortex_m.c:415 cortex_m_debug_entry():
Debug: 523 561 cortex_m.c:164 cortex_m_clear_halt(): NVIC_DFSR 0x9
Debug: 524 564 cortex_m.c:1509 cortex_m_load_core_reg_u32(): load from core reg 0 value 0x0
Debug: 525 565 cortex_m.c:1509 cortex_m_load_core_reg_u32(): load from core reg 1 value 0x0
Debug: 526 567 cortex_m.c:1509 cortex_m_load_core_reg_u32(): load from core reg 2 value 0x0
Debug: 527 568 cortex_m.c:1509 cortex_m_load_core_reg_u32(): load from core reg 3 value 0x0
Debug: 528 569 cortex_m.c:1509 cortex_m_load_core_reg_u32(): load from core reg 4 value 0x0
Debug: 529 571 cortex_m.c:1509 cortex_m_load_core_reg_u32(): load from core reg 5 value 0x0
Debug: 530 572 cortex_m.c:1509 cortex_m_load_core_reg_u32(): load from core reg 6 value 0x0
Debug: 531 573 cortex_m.c:1509 cortex_m_load_core_reg_u32(): load from core reg 7 value 0x0
Debug: 532 575 cortex_m.c:1509 cortex_m_load_core_reg_u32(): load from core reg 8 value 0x0
Debug: 533 576 cortex_m.c:1509 cortex_m_load_core_reg_u32(): load from core reg 9 value 0x0
Debug: 534 577 cortex_m.c:1509 cortex_m_load_core_reg_u32(): load from core reg 10 value 0x0
Debug: 535 578 cortex_m.c:1509 cortex_m_load_core_reg_u32(): load from core reg 11 value 0x0
Debug: 536 579 cortex_m.c:1509 cortex_m_load_core_reg_u32(): load from core reg 12 value 0x0
Debug: 537 581 cortex_m.c:1509 cortex_m_load_core_reg_u32(): load from core reg 13 value 0x20007a90
Debug: 538 582 cortex_m.c:1509 cortex_m_load_core_reg_u32(): load from core reg 14 value 0xffffffff
Debug: 539 584 cortex_m.c:1509 cortex_m_load_core_reg_u32(): load from core reg 15 value 0x8000408
Debug: 540 585 cortex_m.c:1509 cortex_m_load_core_reg_u32(): load from core reg 16 value 0x1000000
Debug: 541 588 cortex_m.c:1509 cortex_m_load_core_reg_u32(): load from core reg 17 value 0x20007a90
Debug: 542 589 cortex_m.c:1509 cortex_m_load_core_reg_u32(): load from core reg 18 value 0x0
Debug: 543 590 cortex_m.c:1563 cortex_m_load_core_reg_u32(): load from special reg 19 value 0x0
Debug: 544 592 cortex_m.c:1563 cortex_m_load_core_reg_u32(): load from special reg 20 value 0x0
Debug: 545 593 cortex_m.c:1563 cortex_m_load_core_reg_u32(): load from special reg 21 value 0x0
Debug: 546 594 cortex_m.c:1563 cortex_m_load_core_reg_u32(): load from special reg 22 value 0x0
Debug: 547 595 cortex_m.c:475 cortex_m_debug_entry(): entered debug state in core mode: Thread at PC 0x8000408, target->state: halted
Debug: 548 595 target.c:1501 target_call_event_callbacks(): target event 0 (gdb-halt)
Debug: 549 595 target.c:1501 target_call_event_callbacks(): target event 1 (halted)
User : 550 595 target.c:1936 target_arch_state(): stm32f7x.cpu: target state: halted
User : 551 595 armv7m.c:553 armv7m_arch_state(): target halted due to debug-request, current mode: Thread
xPSR: 0x01000000 pc: 0x08000408 msp: 0x20007a90
Debug: 552 596 command.c:145 script_debug(): command - ocd_command ocd_command type ocd_stm32f7x.cpu curstate
Debug: 553 596 command.c:145 script_debug(): command - ocd_stm32f7x.cpu ocd_stm32f7x.cpu curstate
Debug: 554 596 command.c:145 script_debug(): command - ocd_command ocd_command type ocd_transport select
Debug: 555 597 command.c:145 script_debug(): command - ocd_transport ocd_transport select
Debug: 556 597 command.c:145 script_debug(): command - ocd_command ocd_command type ocd_stm32f7x.cpu cget -chain-position
Debug: 557 597 command.c:145 script_debug(): command - ocd_stm32f7x.cpu ocd_stm32f7x.cpu cget -chain-position
Debug: 558 597 command.c:145 script_debug(): command - ocd_command ocd_command type ocd_jtag tapisenabled stm32f7x.cpu
Debug: 559 598 command.c:145 script_debug(): command - ocd_jtag ocd_jtag tapisenabled stm32f7x.cpu
Debug: 560 598 command.c:145 script_debug(): command - ocd_command ocd_command type ocd_stm32f7x.cpu arp_waitstate halted 5000
Debug: 561 598 command.c:145 script_debug(): command - ocd_stm32f7x.cpu ocd_stm32f7x.cpu arp_waitstate halted 5000
Debug: 562 600 command.c:145 script_debug(): command - ocd_command ocd_command type ocd_stm32f7x.cpu invoke-event reset-init
Debug: 563 600 command.c:145 script_debug(): command - ocd_stm32f7x.cpu ocd_stm32f7x.cpu invoke-event reset-init
Debug: 564 600 target.c:4256 target_handle_event(): target: (0) stm32f7x.cpu (cortex_m) event: 17 (reset-init) action:
# Configure PLL to boost clock to HSI x 4 (64 MHz)
mww 0x40023804 0x08012008 ;# RCC_PLLCFGR 16 Mhz /8 (M) * 128 (N) /4(P)
mww 0x40023C00 0x00000102 ;# FLASH_ACR = PRFTBE | 2(Latency)
mmw 0x40023800 0x01000000 0 ;# RCC_CR |= PLLON
sleep 10 ;# Wait for PLL to lock
mmw 0x40023808 0x00001000 0 ;# RCC_CFGR |= RCC_CFGR_PPRE1_DIV2
mmw 0x40023808 0x00000002 0 ;# RCC_CFGR |= RCC_CFGR_SW_PLL

# Boost JTAG frequency

1. adapter_khz 8000

adapter_khz 500

Debug: 565 601 command.c:145 script_debug(): command - ocd_command ocd_command type ocd_mww 0x40023804 0x08012008
Debug: 566 601 command.c:145 script_debug(): command - mww ocd_mww 0x40023804 0x08012008
Debug: 568 603 command.c:145 script_debug(): command - ocd_command ocd_command type ocd_mww 0x40023C00 0x00000102
Debug: 569 603 command.c:145 script_debug(): command - mww ocd_mww 0x40023C00 0x00000102
Debug: 571 609 command.c:145 script_debug(): command - ocd_command ocd_command type ocd_mww 0x40023800 16811395
Debug: 572 610 command.c:145 script_debug(): command - mww ocd_mww 0x40023800 16811395
Debug: 574 612 command.c:145 script_debug(): command - ocd_command ocd_command type ocd_sleep 10
Debug: 575 612 command.c:145 script_debug(): command - sleep ocd_sleep 10
Error: 577 623 adi_v5_jtag.c:378 jtagdp_overrun_check(): Invalid ACK (7) in DAP response
Debug: 578 625 adi_v5_jtag.c:563 jtagdp_transaction_endcheck(): jtag-dp: CTRL/STAT 0x88000020
Error: 579 625 adi_v5_jtag.c:567 jtagdp_transaction_endcheck(): Debug regions are unpowered, an unexpected reset might have happened
Error: 580 625 arm_adi_v5.c:495 mem_ap_read(): Failed to read memory and, additionally, failed to find out where
Error: 581 626 target.c:4015 target_mem2array(): mem2array: Read @ 0x40023808, w=4, cnt=1, failed
User : 582 626 command.c:546 command_print(): C:\Ac6\SystemWorkbench\plugins\fr.ac6.mcu.debug_1.8.0.201603291114\resources\openocd\scripts/mem_helper.tcl:6: Error:
in procedure ‘program’
in procedure ‘reset’ called at file “embedded:startup.tcl”, line 478
in procedure ‘ocd_bouncer’
in procedure ‘ocd_process_reset’
in procedure ‘ocd_process_reset_inner’ called at file “embedded:startup.tcl”, line 248
in procedure ‘stm32f7x.cpu’ called at file “embedded:startup.tcl”, line 370
in procedure ‘ocd_bouncer’
in procedure ‘mmw’
in procedure ‘mrw’ called at file “C:\Ac6\SystemWorkbench\plugins\fr.ac6.mcu.debug_1.8.0.201603291114\resources\openocd\scripts/mem_helper.tcl”, line 16
at file “C:\Ac6\SystemWorkbench\plugins\fr.ac6.mcu.debug_1.8.0.201603291114\resources\openocd\scripts/mem_helper.tcl”, line 6

Debug: 583 627 command.c:145 script_debug(): command - ocd_command ocd_command type ocd_stm32f7x.cpu invoke-event reset-end
Debug: 584 628 command.c:145 script_debug(): command - ocd_stm32f7x.cpu ocd_stm32f7x.cpu invoke-event reset-end
Debug: 585 629 adi_v5_jtag.c:563 jtagdp_transaction_endcheck(): jtag-dp: CTRL/STAT 0x88000020
Error: 586 629 adi_v5_jtag.c:567 jtagdp_transaction_endcheck(): Debug regions are unpowered, an unexpected reset might have happened
Debug: 587 629 target.c:1501 target_call_event_callbacks(): target event 0 (gdb-halt)
User : 588 630 target.c:2579 handle_target(): Polling target stm32f7x.cpu failed, trying to reexamine
Debug: 589 630 target.c:1501 target_call_event_callbacks(): target event 21 (examine-start)
Debug: 590 630 arm_adi_v5.c:605 dap_dp_init():
Debug: 591 630 arm_adi_v5.c:638 dap_dp_init(): DAP: wait CDBGPWRUPACK
Debug: 592 630 arm_adi_v5.h:427 dap_dp_poll_register(): DAP: poll 4, mask 0x20000000, value 0x20000000
Debug: 593 632 arm_adi_v5.c:645 dap_dp_init(): DAP: wait CSYSPWRUPACK
Debug: 594 632 arm_adi_v5.h:427 dap_dp_poll_register(): DAP: poll 4, mask 0x80000000, value 0x80000000
Debug: 595 635 arm_adi_v5.c:789 dap_find_ap(): Found AHB-AP at AP index: 0 (IDR=0x74770001)
Debug: 596 637 arm_adi_v5.c:716 mem_ap_init(): MEM_AP Packed Transfers: enabled
Debug: 597 637 arm_adi_v5.c:727 mem_ap_init(): MEM_AP CFG: large data 0, long address 0, big-endian 0
Debug: 598 638 target.c:2226 target_read_u32(): address: 0xe000ed00, value: 0x410fc271
Debug: 599 638 cortex_m.c:1930 cortex_m_examine(): Cortex-M7 r0p1 processor detected
Debug: 600 638 cortex_m.c:1931 cortex_m_examine(): cpuid: 0x410fc271
Debug: 601 639 target.c:2314 target_write_u32(): address: 0xe000edfc, value: 0x01000000
Debug: 602 641 target.c:2226 target_read_u32(): address: 0xe0002000, value: 0x10000080
Debug: 603 641 target.c:2314 target_write_u32(): address: 0xe0002008, value: 0x00000000
Debug: 604 642 target.c:2314 target_write_u32(): address: 0xe000200c, value: 0x00000000
Debug: 605 644 target.c:2314 target_write_u32(): address: 0xe0002010, value: 0x00000000
Debug: 606 645 target.c:2314 target_write_u32(): address: 0xe0002014, value: 0x00000000
Debug: 607 646 target.c:2314 target_write_u32(): address: 0xe0002018, value: 0x00000000
Debug: 608 647 target.c:2314 target_write_u32(): address: 0xe000201c, value: 0x00000000
Debug: 609 649 target.c:2314 target_write_u32(): address: 0xe0002020, value: 0x00000000
Debug: 610 650 target.c:2314 target_write_u32(): address: 0xe0002024, value: 0x00000000
Debug: 611 652 cortex_m.c:2005 cortex_m_examine(): FPB fpcr 0x10000080, numcode 8, numlit 0
Debug: 612 653 target.c:2226 target_read_u32(): address: 0xe0001000, value: 0x40000000
Debug: 613 653 target.c:2314 target_write_u32(): address: 0xe0001028, value: 0x00000000
Debug: 614 655 target.c:2314 target_write_u32(): address: 0xe0001038, value: 0x00000000
Debug: 615 656 target.c:2314 target_write_u32(): address: 0xe0001048, value: 0x00000000
Debug: 616 657 target.c:2314 target_write_u32(): address: 0xe0001058, value: 0x00000000
Debug: 617 658 cortex_m.c:1849 cortex_m_dwt_setup(): DWT dwtcr 0x40000000, comp 4, watch/trigger
Info : 618 659 cortex_m.c:2015 cortex_m_examine(): stm32f7x.cpu: hardware has 8 breakpoints, 4 watchpoints
Debug: 619 659 target.c:1501 target_call_event_callbacks(): target event 22 (examine-end)
Debug: 620 659 target.c:4256 target_handle_event(): target: (0) stm32f7x.cpu (cortex_m) event: 22 (examine-end) action:
# Enable debug during low power modes (uses more power)
# DBGMCU_CR |= DBG_STANDBY | DBG_STOP | DBG_SLEEP
mmw 0xE0042004 0x00000007 0

# Stop watchdog counters during halt
# DBGMCU_APB1_FZ |= DBG_IWDG_STOP | DBG_WWDG_STOP
mmw 0xE0042008 0x00001800 0

Debug: 621 661 command.c:145 script_debug(): command - ocd_command ocd_command type ocd_mww 0xE0042004 7
Debug: 622 661 command.c:145 script_debug(): command - mww ocd_mww 0xE0042004 7
Debug: 624 663 command.c:145 script_debug(): command - ocd_command ocd_command type ocd_mww 0xE0042008 6144
Debug: 625 664 command.c:145 script_debug(): command - mww ocd_mww 0xE0042008 6144
Debug: 627 665 command.c:145 script_debug(): command - ocd_command ocd_command type ocd_echo ** Programming Started **
Debug: 628 665 command.c:145 script_debug(): command - echo ocd_echo ** Programming Started **
User : 630 667 command.c:764 jim_echo(): ** Programming Started **
Debug: 631 667 command.c:145 script_debug(): command - ocd_command ocd_command type ocd_flash write_image erase Debug/3DHUMS_Compact.elf
Debug: 632 667 command.c:145 script_debug(): command - ocd_flash ocd_flash write_image erase Debug/3DHUMS_Compact.elf
Debug: 633 668 cortex_m.c:531 cortex_m_poll(): Exit from reset with dcb_dhcsr 0x1010000
Debug: 634 670 cortex_m.c:235 cortex_m_endreset_event(): DCB_DEMCR = 0x01000000
Debug: 635 672 target.c:2314 target_write_u32(): address: 0xe0002000, value: 0x00000003
Debug: 636 675 target.c:2226 target_read_u32(): address: 0xe0002000, value: 0x10000081
Debug: 637 675 target.c:2314 target_write_u32(): address: 0xe0002008, value: 0x00000000
Debug: 638 676 target.c:2314 target_write_u32(): address: 0xe000200c, value: 0x00000000
Debug: 639 677 target.c:2314 target_write_u32(): address: 0xe0002010, value: 0x00000000
Debug: 640 679 target.c:2314 target_write_u32(): address: 0xe0002014, value: 0x00000000
Debug: 641 680 target.c:2314 target_write_u32(): address: 0xe0002018, value: 0x00000000
Debug: 642 681 target.c:2314 target_write_u32(): address: 0xe000201c, value: 0x00000000
Debug: 643 682 target.c:2314 target_write_u32(): address: 0xe0002020, value: 0x00000000
Debug: 644 684 target.c:2314 target_write_u32(): address: 0xe0002024, value: 0x00000000
Debug: 645 685 target.c:2314 target_write_u32(): address: 0xe0001020, value: 0x00000000
Debug: 646 686 target.c:2314 target_write_u32(): address: 0xe0001024, value: 0x00000000
Debug: 647 687 target.c:2314 target_write_u32(): address: 0xe0001028, value: 0x00000000
Debug: 648 689 target.c:2314 target_write_u32(): address: 0xe0001030, value: 0x00000000
Debug: 649 690 target.c:2314 target_write_u32(): address: 0xe0001034, value: 0x00000000
Debug: 650 691 target.c:2314 target_write_u32(): address: 0xe0001038, value: 0x00000000
Debug: 651 692 target.c:2314 target_write_u32(): address: 0xe0001040, value: 0x00000000
Debug: 652 693 target.c:2314 target_write_u32(): address: 0xe0001044, value: 0x00000000
Debug: 653 694 target.c:2314 target_write_u32(): address: 0xe0001048, value: 0x00000000
Debug: 654 696 target.c:2314 target_write_u32(): address: 0xe0001050, value: 0x00000000
Debug: 655 697 target.c:2314 target_write_u32(): address: 0xe0001054, value: 0x00000000
Debug: 656 698 target.c:2314 target_write_u32(): address: 0xe0001058, value: 0x00000000
User : 658 701 command.c:546 command_print(): auto erase enabled
Debug: 659 701 configuration.c:84 find_file(): found Debug/3DHUMS_Compact.elf
Debug: 660 701 image.c:71 autodetect_image_type(): ELF image detected.
Debug: 661 701 configuration.c:84 find_file(): found Debug/3DHUMS_Compact.elf
Debug: 662 703 target.c:2226 target_read_u32(): address: 0xe0042000, value: 0x10016449
Debug: 663 703 stm32f7x.c:810 stm32x_probe(): device id = 0x10016449
Debug: 664 704 target.c:2226 target_read_u32(): address: 0x40023c14, value: 0xc0ffaafd
Debug: 665 706 target.c:2250 target_read_u16(): address: 0x1ff0f442, value: 0x0400
Info : 666 706 stm32f7x.c:840 stm32x_probe(): flash size probed value 1024
Debug: 667 706 core.c:712 flash_write_unlock(): image_read_section: section = 0, t_section_num = 0, section_offset = 0, buffer_size = 0, size_read = 15120
Debug: 668 706 image.c:480 image_elf_read_section(): load segment 0 at 0x0 (sz = 0x3b10)
Debug: 669 706 image.c:487 image_elf_read_section(): read elf: size = 0x15120 at 0x10000
Debug: 670 707 core.c:712 flash_write_unlock(): image_read_section: section = 1, t_section_num = 1, section_offset = 0, buffer_size = 15120, size_read = 8
Debug: 671 707 image.c:480 image_elf_read_section(): load segment 1 at 0x0 (sz = 0x8)
Debug: 672 707 image.c:487 image_elf_read_section(): read elf: size = 0x8 at 0x20000
Error: 673 707 core.c:47 flash_driver_erase(): failed erasing sectors 0 to 0
Debug: 674 707 command.c:628 run_command(): Command failed with error code -304
Debug: 675 708 command.c:145 script_debug(): command - ocd_command ocd_command type ocd_echo ** Programming Failed **
Debug: 676 708 command.c:145 script_debug(): command - echo ocd_echo ** Programming Failed **
User : 678 710 command.c:764 jim_echo(): ** Programming Failed **
Debug: 679 710 command.c:145 script_debug(): command - ocd_command ocd_command type ocd_shutdown error
Debug: 680 710 command.c:145 script_debug(): command - shutdown ocd_shutdown error
User : 682 711 server.c:611 handle_shutdown_command(): shutdown comm