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SW4STM32 and SW4Linux fully supports the STM32MP1 asymmetric multicore Cortex/A7+M4 MPUs

   With System Workbench for Linux, Embedded Linux on the STM32MP1 family of MPUs from ST was never as simple to build and maintain, even for newcomers in the Linux world. And, if you install System Workbench for Linux in System Workbench for STM32 you can seamlessly develop and debug asymmetric applications running partly on Linux, partly on the Cortex-M4.
You can get more information from the ac6-tools website and download (registration required) various documents highlighting:

System Workbench for STM32

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NUCLEO-L476RG - Error: Whole bank access must start at beginning of bank.

Posted by ganesh80 on 2019-05-01 17:27

I have seen this error discussed in this community before, however I haven’t seen a solution posted. Does anyone know what is causing this error? I am using the NUCLEO-L476RG board.

The following is my log:

11:25:16 **** Programming project stm32L476xx_drivers2 on chip ****
“C:\Ac6\SystemWorkbench\plugins\fr.ac6.mcu.externaltools.openocd.win32_1.23.0.201904120827\tools\openocd\bin\openocd.exe” -f stm32.flash.4377737752302794891.cfg -s “C:\Users\Ganesh\Documents\Ganesh_Documents\IntroToEmbeddedSystems\UdemyCourse\OpenSTM32SystemWorkbench\Workspace\stm32L476xx_drivers2” -s “C:\Ac6\SystemWorkbench\plugins\fr.ac6.mcu.debug_2.5.0.201904120827\resources\openocd\st_scripts” -c “program Debug/stm32L476xx_drivers2.elf verify reset ” -c shutdown
Open On-Chip Debugger 0.10.0+dev-00021-g524e8c8 (2019-04-12-08:48)
Licensed under GNU GPL v2
For bug reports, read
http://openocd.org/doc/doxygen/bugs.html
srst_only separate srst_nogate srst_open_drain connect_assert_srst
Info : The selected transport took over low-level target control. The results might differ compared to plain JTAG/SWD
padded zone erase set to 1
adapter speed: 8000 kHz
adapter_nsrst_delay: 100
Info : clock speed 8000 kHz
Info : STLINK v2.1 JTAG v33 API v2 M25 VID 0x0483 PID 0x374B
Info : using stlink api v2
Info : Target voltage: 3.263810
Info : Unable to match requested speed 8000 kHz, using 4000 kHz
Info : Stlink adapter speed set to 4000 kHz
Info : STM32L476RGTx.cpu: hardware has 6 breakpoints, 4 watchpoints
Info : Listening on port 3333 for gdb connections
target halted due to debug-request, current mode: Thread
xPSR: 0x01000000 pc: 0x08000714 msp: 0x20018000
Info : Unable to match requested speed 8000 kHz, using 4000 kHz
Info : Stlink adapter speed set to 4000 kHz
Info : Unable to match requested speed 8000 kHz, using 4000 kHz
adapter speed: 4000 kHz

    • Programming Started **

auto erase enabled
Info : Device id = 0x10076415
Info : STM32L4xx flash size is 1024kb, base address is 0x8000000
Info : Erase the padded zone before the write
Error: Whole bank access must start at beginning of bank.
target halted due to breakpoint, current mode: Thread
xPSR: 0x61000000 pc: 0x20000050 msp: 0x20018000
wrote 4096 bytes from file Debug/stm32L476xx_drivers2.elf in 0.320144s (12.494 KiB/s)

    • Programming Finished **
    • Verify Started **

target halted due to breakpoint, current mode: Thread
xPSR: 0x61000000 pc: 0x2000002e msp: 0x20018000
target halted due to breakpoint, current mode: Thread
xPSR: 0x61000000 pc: 0x2000002e msp: 0x20018000
verified 3520 bytes in 0.210437s (16.335 KiB/s)

    • Verified OK **
    • Resetting Target **

shutdown command invoked

11:25:19 Build Finished (took 2s.341ms)

Reads: 2905
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