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Zephyr project on STM32

   Zephyr Workbench, a VSCode extension to manage Zephyr on STM32.
It enables users to easily create, develop, and debug Zephyr applications.
Main features:
  • Install host dependencies.
  • Import toolchain and SDK.
  • Create, configure, build and manage apps.
  • Debug STM32.
You can directly download it from the VSCode marketplace
For more details, visit the Zephyr Workbench

System Workbench for STM32

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Single Step Debugging while a timer is active

Posted by grunzasr on 2016-06-30 19:22

The method I used to use was to define something like:

define hook-step
mon cortex_m maskisr on
end

define hookpost-step
mon cortex_m maskisr off
end



in my .gdbinit directory from which I launched arm-none-eabi-gdb.


Is there some way to do something similar using SW4STM32? I’m trying to debug an STM32F745 project but once the FreeRTOS time base timers are started, single stepping keeps jumping to the timer ISR.

Reads: 13733
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Posted by tarek bouchkati on 2016-07-01 12:13 Tunisia

Hello Steven,

All you have to do is to place your .gdbinit is the same directory of your “.cproject”
eg: ~\STM32Cube_FW_F7_V1.4.0\Projects\STM32F746ZG-Nucleo\Examples\GPIO\GPIO_IOToggle\SW4STM32\STM32746ZG_Nucleo

Regards,
Tarek

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Posted by uzairo89 on 2016-07-05 13:15
Tarek, can you elaborate a bit? I also have a problem with the timer interupt affecting single-stepping. But I don’t know what gdbint is.
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Posted by tarek bouchkati on 2016-07-11 11:13 Tunisia

Uzair,

context :
supposing you have a project named MyProj under the following folder “~/.../MyFolder/SW4STM32/MyProj/”
within this folder you have a file named “.cproject”

the “.gdbinit” is a file that you have to create if you need to inject some modifications/hooks of normal gdb behaviour (while debugging)

in this case we have created a “.gdbinit” file within the same folder as the “.cproject” with the follwing content (hook) :

define hook-step
mon cortex_m maskisr on
end

define hookpost-step
mon cortex_m maskisr off
end

these hooks disable interrupts before the step and enable them after the step operation

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Posted by uzairo89 on 2016-07-12 06:28

Tarek,
Thank you for the explanation. If the hooks disable the interrupts, does it affect the program flow? Is it possible that some interrupts are missed while the stepping operation is ocurring?

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Posted by tarek bouchkati on 2016-07-12 10:07 Tunisia

Please find below an extract from openocd documentation >> 16.5.5 Cortex-M specific commandsQuestion

Command: cortex_m maskisr (auto|on|off)

Control masking (disabling) interrupts during target step/resume.

The auto option handles interrupts during stepping a way they get served but don’t disturb the program flow. The step command first allows pending interrupt handlers to execute, then disables interrupts and steps over the next instruction where the core was halted. After the step interrupts are enabled again. If the interrupt handlers don’t complete within 500ms, the step command leaves with the core running.

Note that a free breakpoint is required for the auto option. If no breakpoint is available at the time of the step, then the step is taken with interrupts enabled, i.e. the same way the off option does.

Default is auto.

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Posted by devcal on 2016-07-14 12:59

Hi

Tarek, thank you for your description.
I have created the .gdbinit file. And it seams to work. since by each step I become the same error: invalid command name “cortex_m”

First I thought it was something wrong with this file. But then I send the command “cortex_m maskisr on “ directly to the OCD and become the same error: invalid command name “cortex_m”

I’m using:
System Workbench for STM32 version 1.7.0.02162121829 with OpenOCD V 1.9.0.20165241146
my Target is a STM32F74bIGT
and debugger: ST-LinkV2 Firmware: V2.J27.S6
My OCD .config file contains the following:

  1. This is an ST5100_MA board with a single STM32F746IGTx chip.
  2. Generated by System Workbench for STM32


source find interface/stlink-v2.cfg

hla_serial V?o#gwUV’8#g

  1. hla_serial V?p#gwUVUG#g

transport select hla_swd

set WORKAREASIZE 0x50000

source find target/stm32f7x.cfg

  1. use hardware reset, connect under reset

reset_config srst_only srst_nogate


Does anyone knows what I’m doing wrong?

Regards.
Dev.

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