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SW4STM32 and SW4Linux fully supports the STM32MP1 asymmetric multicore Cortex/A7+M4 MPUs

   With System Workbench for Linux, Embedded Linux on the STM32MP1 family of MPUs from ST was never as simple to build and maintain, even for newcomers in the Linux world. And, if you install System Workbench for Linux in System Workbench for STM32 you can seamlessly develop and debug asymmetric applications running partly on Linux, partly on the Cortex-M4.
You can get more information from the ac6-tools website and download (registration required) various documents highlighting:

System Workbench for STM32


OpenOCD stops working when semihosting enabled

Hi All,

I was wondering if anybody could help with a strange problem, first time I’ve encountered this kind of issue.

I just recently got my hands on the beefy NUCLEO-H743ZI board. Started setting it up as I usually do, by enabling semihosting.

And as soon as I do that, OpenOCD crashes, gives bunch of errors and doesn’t work anymore. The execution doesn’t even start. And I can’t send run command either.

Funny enough, I re-flashed the stlink to jlink (I used JlinkGDB not openocd) to see if I can reproduce the same issue. And behold I have a similar issue, the difference is that compiled code runs, semihosting also works and prints in the console, BUT none of the breakpoints work, also symbols are not loaded, if I pause the execution I only get machine code.

All is solved by disabling semihosting. For both jlink and openocd with stlink


I’m very puzzled, I haven’t had this problem on none of my previous dev boards F103RB, F429ZI and F207ZG. All 3 just works.

Here is OpenOCD output:
Open On-Chip Debugger 0.10.0-dev-00010-g96aab7b (2018-07-13-06:37)
Licensed under GNU GPL v2
For bug reports, read
http://openocd.org/doc/doxygen/bugs.html
Warn : Could not determine executable path, using configured BINDIR.
srst_only separate srst_nogate srst_open_drain connect_assert_srst
Info : The selected transport took over low-level target control. The results might differ compared to plain JTAG/SWD
adapter_nsrst_delay: 100
adapter speed: 1800 kHz
Info : clock speed 1800 kHz
Info : STLINK v2.1 JTAG v31 API v2 M21 VID 0x0483 PID 0x374B
Info : using stlink api v2
Info : Target voltage: 3.242270
Info : Stlink adapter speed set to 1800 kHz
Info : STM32H743ZITx.cpu: hardware has 8 breakpoints, 4 watchpoints
Info : accepting ‘gdb’ connection on tcp/3333
target halted due to debug-request, current mode: Thread
xPSR: 0x01000000 pc: 0x08004764 msp: 0x20020000
Info : Stlink adapter speed set to 4000 kHz
adapter speed: 4000 kHz
Info : Device: STM32H7xx 2M
Info : flash size probed value 2048
Info : STM32H flash has dual banks. Bank (0) size is 1024kb, base address is 0x8000000
Info : Device: STM32H7xx 2M
Info : flash size probed value 2048
Info : STM32H flash has dual banks. Bank (1) size is 1024kb, base address is 0x8100000
target halted due to debug-request, current mode: Thread
xPSR: 0x01000000 pc: 0x08004764 msp: 0x20020000
Info : Stlink adapter speed set to 4000 kHz
adapter speed: 4000 kHz
Info : Padding image section 0 with 8 bytes
target halted due to breakpoint, current mode: Thread
xPSR: 0x61000000 pc: 0x20000052 msp: 0x20020000
target halted due to debug-request, current mode: Thread
xPSR: 0x01000000 pc: 0x08003da0 msp: 0x20020000
Info : Stlink adapter speed set to 4000 kHz
adapter speed: 4000 kHz
Error: address + size wrapped (0xffffffff, 0x00000004)
Error: address + size wrapped (0xffffffff, 0x00000002)
Error: address + size wrapped (0xffffffff, 0x00000004)
Error: address + size wrapped (0xffffffff, 0x00000002)




I’m enabling semihosting by adding these flags to linker:
-specs=rdimon.specs -lc -lrdimon

And obviously, defining “extern void initialise_monitor_handles();” and calling it in my main function at the top.


Could my board be faulty? I’m not sure what are D caches or I caches in cortex m7, maybe those are to blame? Is there a bug?
Any help would be appreciated, thanks.